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CMOS bootstrapped output driver method and circuit

  • US 5,128,563 A
  • Filed: 11/28/1990
  • Issued: 07/07/1992
  • Est. Priority Date: 11/28/1990
  • Status: Expired due to Term
First Claim
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1. An output driver circuit having an output pad, digital circuit inputs comprising an input signal, an inverse signal of said input signal, a control signal, and supply and ground nodes, said supply and ground nodes connectable to supply and ground potentials respectively, said digital circuit inputs having high and low logic levels, wherein the output driver circuit comprises:

  • a) a push-pull transistor configuration having a pull-up transistor circuit connectable to said supply potential, said pull-up transistor circuit being a CMOS transistor arrangement, said CMOS transistor arrangement comprising serially connected NMOS and PMOS transistors, the PMOS transistor being gated by the input signal after inversion of the input signal through an inverter, the NMOS transistor gated in at least two increments by a bootstrapped configuration at a gate node, said bootstrapped configuration accepting the input signal and the inverse signal such that the NMOS and the PMOS of said CMOS receive complementary gate signals resulting in duplicate switching wherein both transistors are off when the input signal has said low logic level and both transistors are on when the input signal has said high logic level;

    b) a pull-down transistor connectable to said ground potential, said pull-down transistor being an NMOS having a drain connected serially at said series connection to a source of the NMOS of said CMOS transistor arrangement and having its source connectable to said ground potential, the NMOS of said pull-down transistor gated by said control signal such that a high logic level control signal transfers a low logic level input signal to the output pad and a low logic level control signal transfers a high impedance to the output pad when said input signal has said low logic level and transfers said high logic level to the output pad when said input signal has said high logic level, said pull-up and pull-down transistors having a series connection, the output pad connected in parallel with said pull-down transistor from said series connection to said ground potential; and

    c) said pull-down transistor further comprises at least two parallel connected NMOS, said parallel connected NMOS having a common source at said ground potential and a common drain at said series connection and being gated by said control signal.

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