Adaptive phase lock loop system

• US 5,128,625 A
• Filed: 09/12/1990
• Issued: 07/07/1992
• Est. Priority Date: 02/14/1990
• Status: Expired due to Term

• Current Assignee: KDDI Corporation
• Original Assignee: Kokusai Denshi Denwa Company Limited (KDDI Corporation)
• Inventors: Muratani, Takuro, Yatsuzuka, Yohtaro
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Tran, Sinh N.
• Application Number:
  US07/581,820
• Time in Patent Office: 664 Days
• Field of Search: 328/155, 307/511, 307/516, 307/527, 455/260, 455/265, 375/97, 331/25
• US Class Current: 327/156
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H03L 7/113 using frequency discriminator

Abstract

A phase lock loop for a digital input signal has a phase detector, a loop filter, a digital voltage controlled oscillator (VCO), an initial phase difference calculator, a center frequency difference calculator and an input buffer memory. In an initial training mode prepared in the PLL operation, an optimum initial phase and an optimum center frequency of the VCO to complete a lock-in state is searched for the input signal stored in the buffer memmory. By estimating the initial phase difference and the center frequency difference between the input signal and the VCO output with repetative kick-offs in calculators, optimum values mentioned above are obtained. In a normal operation mode as a second mode in which the PLL operates normally as a conventional PLL, a phase lock operation between the VCO outut as the reference signal and the input signal in the buffer memory is carried out after the PLL is kicked off with the optimum initial phase and the optimum center frequency determined in the initial training mode.

Claims

1. An adaptive phase lock loop system comprising:

a buffer memory for storing a digital input signal;

a phase detector for comparing a phase of the digital input signal and a phae of a reference signal;

a loop filter coupled with an output of said phase detector;

a digital voltage controlled oscillator providing a VCO output as the reference signal to said phase detector, said digital voltage controlled oscillator including

a center frequency generator providing a center frequency of said digital voltage controlled oscillator,

a first adder to provide a sum of an output of said loop filter and an output of said center frequency generator,

an accumulator accumulating an output of said first adder,

an initial phase generator providing an initial phase of said digital voltage controlled oscillator,

a second adder providing a sum of an output of said accumulator and an output of said initial phase generator,

a cosine converter converting an output of said second adder to a cosine waveform for providing the reference signal of the VCO output,

an initial phase difference caclulator, coupled with the output of said loop filter, said initial phase difference calculator updating the initial phase output fromm said initial phase generator,

a center frequency difference calculator, coupled with the output of said loop filter, said initial phase difference calculator updating the initial phase output from said initial phase generator according to the output of said loop filter,

a center frequency difference calculator, coupled with the output of said loop filter, said center frequency difference calculator updating the center frequency output from said center frequency generator accordiing to the output of said loop filter, and

a mode control means for switchin an operation state between an initial training mode and a normal opeation mode;

wherein said initial training mode repetitively adjusts the initial phase and the center frequency of said initial phase difference calculator and said center frequency different calculator so that the initial phase and the center frequency become optimum to complete a lock-in state for the input signal of said buffer memory, respectively, and said normal operation mode providing a reference signal of the VCP output so that said reference signal is phase-locked with the input signal by using the initial phase and center frequency optimized in said initial training mode.

2. An adaptive phase lock loop system according to claim 1, wherein said initial training mode is switched to said normal operation mode when an initial phase error obtained from the output of said loop filter in said initial phase difference calculator and a center frequency error obtained from the output of said loop filter in said center frequency difference calcultor are less than a predetermiend threshold.

3. An adaptive phase lock loop system according to claim 1, wherein said initial training mode is switched to said normal operation mode when updatings of the initial phase and the center frequency of said digital voltage controlled oscillator in the initial training mode is carried out a predetermined number of times.

4. An adaptive phase lock loop system according to claim 1, wherein the center frequency and the initial phase of the digital voltage controlled oscillator are updated at repetitive kick-offs for a same input signal in said buffer memory by estimating an initial phase difference from said initial phase error and a center frequency difference from said center frequency error in said initial training mode.

5. An adaptive phase lock loop system according to claim 1, wherein a lowpass filter is provided between the output of said phase detector and an input of said loop filter.

6. An adaptive phase lock loop system according to claim 1, wherein a bandwidth of a PLL loop is switched narrower when said initial training mode is switched to said normal operation mode.

7. An adaptive phase lock loop system according to claim 1, wherein a bandwidth of a PLL loop is switched narrower in every trial operation in said initial training mode.

8. An adaptive phase lock loop system according to claim 1, wherein a bandpass filter is provided at an input of said buffer memory, an initial center frequency of said digital voltage controlled oscillator in an adaptive PLL coupled with said bandpass filter is provided by the center frequency of said bandpass filter, a carrier component is detected by obtaining the center frequency of said digital voltage controlled oscillator in which a lock-in state is detected by a quadrature phase component or an inphase component, and at least one of a center frequency and/or bandwidth of said bandpass filter is adjusted based upon the center frequency of said digital voltage controlled oscillator.

9. An adaptive phase lock loop system according to claim 1, wherein a bandpass filter is provided at an input of said buffer memory, initial center frequencies of said digital voltage controlled oscillator in an adaptive PLL coupled with said bandpass filter are predetermined in the initial training mode, a carrier component is detected by obtaining a same center frequency for different initial center frequencies or a minimum frequency difference between those center frequencies, and at least one of center frequency and/or bandwidth of said bandpass filter is adjusted based upon the center frequency of said digital voltage controlled oscillator.

10. An adaptive phase lock loop system according to claim 1, wherein bandpass filter is provided at an input of said buffer memory for dividing a bandwidth of the input signal into a plurality of bandwidths, an initial center frequency of said digital voltage controlled oscillator in an adaptive PLL coupled with the bandpass filter is provided by the center frequency of each band, a carrier component is detected through the bandpass filter which has a same center frequency as that of another band or has a minimum frequency different between those bands, or is related to said adaptive PLL in which a lock-in state is detected by a quadrature phase component or an inphase component, and at least one of center frequency and/or bandwidth of said bandpass filter is adjusted based upon a center frequency of said digital voltage controlled oscillator of said related adaptive PLL.

11. An adaptive phase lock loop system according to claim 8, wherein said quadrature phase component or said inphase component of the input digital signal of said adaptive PLL and the reference signal is compared in a quadrature phase detector or said phase detector to detect the lock-in state.

12. An adaptive phase lock loop system according to claim 8, wherein at least one of center frequency and bandwidth of said bandpass filter and the center frequency of said digital voltage controlled oscillator in said initial training mode are initially adjusted based upon frequency analyzed through spectrum analysis of an output of said bandpass filter.

13. An adaptive phase lock system according to claim 1, wherein the input signal is divided into a plurality of time sequential frames and said initial training mode is carried out for each frame.

14. An adaptive phase lock loop system according to claim 1, wherein said normal operation mode is switched to said initial training mode, when an unlocked condition occurs during said normal operation mode.

15. An adaptive phase lock loop system according to claim 8, wherein at least one of center frequency and bandwidth of said bandpass filter is adjusted according to the center frequency of said digital voltage controlled oscillator in both of said initial training mode and said normal operation mode.

16. An adaptive phase lock loop system according to claim 10, wherein a carrier frequency component of the input signal resides in a band in which an output of a related bandpass filter has a most at a beginning time of the initial training mode.

17. An adaptive phase lock loop system according to claim 1, wherein said initial phase difference calculator provides an average value in a block of the output of said loop filter as an intial phase error for a first duration in said initial training mode, and said center frequency difference calculator provides an average value in a block of output of said loop filter for a second duration which follows said first duration.

18. An adaptive phase lock loop system according to claim 17, wherein said initial phase difference calculator provides an average value of the output of said loop filter for 1-10 samplings after kick-off as an initial phase error and said center frequency difference calculator provides an average value of output level of said loop filter for 30-40 samples as a center frequency error.

19. An adaptive phase lock loop system according to claim 1, wherein said center frequency difference calculator provides an average value in a block of output of said loop filter for a duration after kick-off and said initial phase difference calculator provides an initial phase error calculated by using the center frequency, a center frequency error and the output of said accumulator for said duration.

20. An adaptive phase lock loop system according to claim 1, wherein the center frequency of said center frequency generator is set by a predetermined value or a value given by a spectrum analyzer.

21. An adaptive phase lock loop system according to claim 1, wherein said center frequency generator and said initial phase generator provide DC level outputs corresponding to frequency and phase, respectively.