Semiconductor integrated circuit fabrication yield improvements

• US 5,128,737 A
• Filed: 03/02/1990
• Issued: 07/07/1992
• Est. Priority Date: 03/02/1990
• Status: Expired due to Fees

• Current Assignee: Silicon Dynamics, Inc.
• Original Assignee: Silicon Dynamics, Inc.
• Inventors: van der Have, Leonard A.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Potter, Roy
• Application Number:
  US07/487,768
• Time in Patent Office: 858 Days
• Field of Search: 357/40, 357/71, 357/23.7, 365/96, 365/200, 371/22.3, 371/25.1
• US Class Current: 257/503
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Microelectronic integrated circuit fabrication yield is improved through architecture which provides for the search and identification and avoidance of electronic malfunctions in wafer sub-circuits, each of which perform an identical function, such as memory. A processor contained within each wafer performs these search, identification and repair functions via communication pathways (busses) formed on the wafer. The processor records the location and type of electronic defects within each sub-circuit and reconfigures the balance of the circuitry included within the overall circuit to provide for a useful overall electronic circuit function using the sub-circuit building blocks.

Claims

1. A wafer interconnect system for distribution of power to circuits or devices fabricated on said wafer and for interconnecting said circuits comprising:

a) a wafer substrate;

b) an active device layer formed on said substrate upon which regions of devices are formed;

c) a first patterned insulator layer formed over said device layer;

d) a first patterned conductive layer formed over said first insulator layer with a first set of contacts extending between said first conductive layer and device layer for interconnecting devices in said active device layer via said first conductive layer;

e) a second patterned insulator layer formed over said first conductor layer;

f) a second patterned conductive layer formed over said second insulator layer with a second set of contacts extending between said second conductive layer and device layer for interconnecting devices in said active device layer via said second conductive layer;

g) a third patterned insulator layer formed over said second conductive layer;

h) a third substantially unpatterned conductive layer formed over said third insulator layer for applying a common voltage to a plurality of a third set of contacts coupled to said device layer;

i) a protective layer formed over said third conductive layer; and

j) an insulator formed between said active device layer and said substrate and resistance regions formed in said active device layer and extending through said insulator on one side and to one or more of said contacts on another side and wherein one or more of the resistance regions is contiguous with the substrate and the substrate is doped to be highly conductive for coupling power to the contiguous resistance regions.

2. The system of claim 1 wherein the resistance of said regions is low enough to provide current flow to operate the devices in the active device layer to which the resistance regions are connected, yet high enough to not impair operation of portions of the wafer interconnect system other than where the devices are located should the resistance region become connected to such other portions.

3. The system of claim 2 wherein the bulk resistivity of the substrate is between about 0.005 Ohm-centimeter and 0.1 Ohm-centimeter.

4. The system of claim 1 wherein the conductive layers are formed of metals taken from the group consisting of aluminum, copper and gold.

5. The system of claim 1 wherein the conductive layers are formed of doped polysilicon.