Arithmetic unit having multiple accumulators

• US 5,128,888 A
• Filed: 04/02/1990
• Issued: 07/07/1992
• Est. Priority Date: 04/02/1990
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Tamura, Glenn A., Sobel, Prem
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US07/504,127
• Time in Patent Office: 827 Days
• Field of Search: 364/754, 364/736, 364/748, 364/730
• US Class Current: 708/508
• CPC Class Codes: G06F 2207/3884 Pipelining
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence

Abstract

An arithmetic logic unit includes structure for calculating in at least two stages, this structure including substructure for calculating in each of the at least two stages at least partially at the same time and substructure for ensuring the substructure for calculating in each of the at least two stages performs only one calculation at a time. Accumulators that work with pipe stages of a floating point unit may form all of part of the calculating structure. A method of performing calculations includes the steps of separating the calculations into at least two stages and separately accumulating the results of the stages using at least two accumulators, one each accumulator for each calculation at each of the at least two stages.

Claims

1. A pipelining floating point processor comprising:

first and second arithmetic operation units;

means for providing input operands to said first and second arithmetic operation units;

at least two accumulators for storing the results of arithmetic operations performed by said first arithmetic operation unit;

means for providing the results stored in said at least two accumulators as accumulated input operands to said second arithmetic operation unit;

first staging means for sequencing said input operands and said accumulated input operands to said second arithmetic unit; and

second staging means for latching intermediate results of arithmetic operations performed by said first arithmetic operation unit using said input operands and intermediate results produced by said second arithmetic operation unit using said input operands and said accumulated operands;

wherein said first and second staging means and at least two said accumulators provide for the pipelining of compound arithmetic operations performed by said floating point processor using said input and accumulated operands through said floating point processor.

2. A pipelined floating point processor as recited in claim 1, further comprising calculation error detecting means.

3. A pipelined computer arithmetic unit as recited in claim 2, wherein said calculation error detecting means comprises an ORed status register.

4. A pipelining floating point processor comprising:

a floating point multiply unit having first and second inputs and an output;

a floating point add unit having input means and an output;

means for providing input operands to said multiply and add units;

at least two accumulators for storing the results of arithmetic operations performed by said multiply and add units;

means for providing the results stored in said at least two accumulators as accumulated operands to said multiply and add units; and

staging means for sequencing said input operands, results produced by said multiply and add units using said input operands, and results produced by said multiply and add units using said input operands and said accumulated operands.

5. A pipelining floating point processor as recited in claim 4, further comprising calculation error detecting means.

6. A piplining floating point processor as recited in claim 5, wherein said calculation error detecting means comprises an ORed status register.

7. A pipelining floating point processor comprising:

a floating point multiply unit having first and second inputs and an output;

a floating point add unit having first and second inputs and an output;

means for providing input operands to said multiply and add units;

at least two accumulators for storing the results of arithmetic operations performed by said multiply and add units, said at least two accumulators arranged in an interleaved fashion between stages of multiply and add loops arising during operation of the multiply and add units respectively;

means for providing the results stored in said at least two accumulators as accumulated operands to said multiply and add units; and

staging means for sequencing said input operands, results produced by said multiply and add units using said input operands, and results produced by said multiply and add units using said input operands and said accumulated operands.

8. A pipelining floating point processor as recited in claim 7, further comprising calculation error detecting means.

9. A pipelining floating point processor as recited in claim 8, wherein said calculation error detecting means comprises an ORed status register.