Wired microcircuit card and a method for transactions between a corresponding wired microcircuit card and a terminal

• US 5,128,997 A
• Filed: 07/17/1990
• Issued: 07/07/1992
• Est. Priority Date: 07/19/1989
• Status: Expired due to Term

• Current Assignee: French State Represented By The Minister of Post Telecommunications and Space (Centre National D'Etudes Des Telecommunications
• Original Assignee: Centre National D'Etudes Des Telecommunications
• Inventors: Girault, Marc, Pailles, Jean-Claude
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): CAIN, DAVID C
• Application Number:
  US07/554,122
• Time in Patent Office: 721 Days
• Field of Search: 380/23, 380/24, 380/25, 235/380-382.5
• US Class Current: 705/66
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/357 Cards having a plurality of specified features
• CPC Class Codes: G06Q 20/3672 initialising or reloading thereof
• CPC Class Codes: G06Q 20/3676 Balancing accounts
• CPC Class Codes: G06Q 20/40975 using encryption therefor
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/0866 by active credit-cards adapted therefor G07F7/1008 takes precedence
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Abstract

The invention concerns a microcircuit card of the kind comprising:

a communication interface;

an internal memoryp

a wired processor unit allowing this internal memory to be addressed from the outside.

According to the main characteristic of the invention, provision is made for a secret internal memory zone not addressable from the outside, and the processor unit comprises a wired circuit capable of using the contents of the secret memory for establishing a first serial cryptographic function of two operands and means reacting to the interrogation of predetermined addresses of the internal memory, accompanied by a keyword by applying this keyword and the output of the internal memory as operands of the wired circuit, whilst the output of the wired circuit is applied to the interface.

Claims

1. A microcircuit card, comprising:

communication interface means (7);

first internal memory means (11) having an output (20);

second (40) internal memory means;

wired circuit means (30) capable of using the contents of said second internal memory means (40) for establishing a first serial cryptographic function of two operands; and

logic control means responsive to interrogation of predetermined addresses of said first internal memory means (11) accompanied by a keyword (19) for applying said keyword (19) and the output (20) of the first internal memory means as operands of the wired circuit means (30), respectively, and for applying an output of the wired circuit means (30) to said communication interface means (7).

2. A microcircuit card according to claim 1, wherein said wired circuit means includes:

a) a first logic operator (31) having two inputs which respectively receive the keyword (19) and the output of said first internal memory means (20), and an output (35); and

b) a retardation logic circuit having input means (32), output means 42, and retardation means forming a loop between outputs and inputs of the second internal memory means (40), said input means (32) receiving respectively the output (35) of the first logic operator (31) and the outputs (38) of the retardation means, said output means (42) having inputs which respectively receive the outputs (38) of the retardation means, and an output (39) which provides the output of the wired circuit.

3. A card according to claim 2, wherein said input means of the retardation logic circuit comprise a second logic operator receiving on the one hand the output of the first operator and on the other hand an output of said retardation means, and wherein at least said second operator is of the binary equiprobable type, such as an EXCLUSIVE OR element.

4. A card according to claim 3, wherein said retardation means comprise a plurality of loop-mounted flip-flops between the outputs and the address inputs of the secret memory, at least one of said loop-mounted flip-flops receiving the output of said second logic operator the second logic operator itself receiving on the one hand the output of the first operator and on the other hand an output of the secret memory, whilst one of said flip-flops provides the output of the wired circuit.

5. A card according to claim 3, wherein said first and second logic operators are both of the EXCLUSIVE OR type.

6. A card according to claim 1, wherein said keyword is a variable coming from said communication interface means.

7. A card according to claim 1, wherein said internal memory means comprises:

identification bits of the card;

value bits to which there is assigned a unit value that is consumable by writing thereon; and

signature bits of the card.

8. A card according to claim 7, wherein said signature bits introduced into said internal memory means are the result of an encoding by a second secret cryptographic function externally from the card, and having the output of the internal memory means as the operand.

9. A card according to claim 7, wherein said signature bits introduced into said internal memory means are the result of an encoding by a second cryptographic function externally of the card, and having the identification bits and value bits as operands.

10. A card according to claim 1, wherein said first internal memory means is a memory with a permanent EPROM type electrically non-erasable entry mode.

11. A card according to claim 1, wherein said first internal memory means is a memory with a permanent EEPROM type erasable and electrically renewable entry mode.

12. A card according to claim 1, wherein the secret memory is a permanent-entry memory.

13. A card according to claim 1, wherein the secret memory is a permanent-entry memory of the PROM type having a fixed binary content.

25. A wired microcircuit card according to claim 1, for implementing the method according to claim 18, and further including:

an EXCLUSIVE OR operator having a first input receiving the signature bits before the transaction and a second input receiving the encoded signal, and

a storage register having an input connected to the output of the EXCLUSIVE OR operator and an output connected to the output of said internal memory means.

26. A wired microcircuit card according to claim 1, for the implementation of the method according to claim 19, and further including:

an adding operator having a first input receiving the bits representing the sum of the transaction coming from the terminal, a second input connected to the output of said internal memory means and a first output connected to the output of said internal memory means; and

a holding flip-flop forming a loop between the inputs and outputs of the adding operator.

27. A wired microcircuit card according to claim 1, for the implementation of the method according to claim 21, wherein the value bits are encoded by a third cryptographic function specific to the card.

28. A wired microcircuit card according to claim 1, for the implementation of the method according to claim 22, wherein said internal memory means includes a reloading counter.

14. In a method for transactions between at least one terminal and at least one wired microcircuit card capable of cooperating with this terminal, the improvement comprising the following steps:

a) providing the card;

with communication interface means,

with internal memory means,

with a wired processor unit allowing said internal memory means to be externally addressed;

b) making provision in the card for an internal memory zone not externally addressable;

c) prestoring in the card;

identification bits of the card

value bits to which there is allocated a unit value that can be used up by writing thereon; and

signature bits of the card;

d) providing the processor unit of the card with a wired circuit capable of using the contents of the internal memory zone for establishing a first serial cryptographic function of the two operands;

e) during a validation request for a transaction assumed to be coming from the card,

e1) receiving at the terminal the output of said internal memory means;

e2) providing the terminal with means capable of generating a keyword;

e3) transmitting the keyword from the terminal;

e4) calculating at the card the transform of the keyword and of the output of said internal memory means by the first cryptographic function;

e5) receiving from the card said transform by the first cryptographic function;

e6) calculating at the terminal the transform of the keyword and of the output of said internal memory means by the first cryptographic function; and

e7) deciding the validation according to the comparison of the transform received from the card and the transform calculated by the terminal.

15. A method according to claim 14, wherein;

in the card, the signature bits serve together with the keyword as the operands for the first cryptographic function.

16. A method according to claim 14, wherein the signature bits introduced into the card are the transform of a second cryptographic function externally of the card, and having the output of said internal memory means as the operand.

17. A method according to claims 14, and further including the step of providing the terminal with means capable of executing a second cryptographic function having the output of the internal memory as operand, whilst during a validation request for a transaction, said step e1) includes, moreover, the step formed by calculating at the terminal the signature bits together with the transform of the output of the internal memory by the second cryptographic function;

and wherein step e6) comprises calculating at the terminal the transform of the first cryptographic function having as operands the keyword and the transform of the second cryptographic function, that is to say the signature bits thus calculated by the terminal.

18. A method according to claim 14, wherein the wired microcircuit card holds at least value bits having a predetermined value, intended to be processed by the terminal to validate the transaction according to chosen criteria, and wherein said method comprises the following steps after the transaction has been concluded;

a) obtaining at the terminal the value bits after the transaction;

b) comparing at the terminal the value bits after the transaction with the value bits before the transaction;

c) if the value bits after the transaction exceed the value bits before the transaction, calculating at the terminal the transform of the identification bits and of the value bits after the transaction by the second cryptographic function;

d) displacing the transform thus calculated by the second cryptographic function by a binary element according to a circular permutation;

e) obtaining an intermediate encoded signal by the EXCLUSIVE OR sum of the transform obtained by the second cryptographic function calculated before the transaction and of the transform by the second cryptographic function calculated after the transaction and itself displaced according to the circular permutation;

f) transmitting from the terminal the value bits after the transaction;

g) transmitting from the terminal the said intermediate encoded signal;

h) entering into the memory the value bits after the transaction;

i) storing in the card the EXCLUSIVE OR sum of the signature bits before the transaction and of the intermediate coded signal;

j) entering into the memory the signature bits after the transaction by means of the said EXCLUSIVE OR sum thus stored.

19. A method according to claim 14, for updating of the value bits after the transaction, and further comprising:

a) transmitting from the terminal the bits representing the amount of the transaction;

b) comparing the bits representing the amount with the value bits;

c) subtracting the bits representing the amount from the value bits; and

d) positioning an indicator according to the subtraction sign.

20. A method according to claim 14, wherein each value bit is associated with a unit value variable according to the weighting of the bit, and wherein the value bits are used up by an irreversible entry from 0 to 1.

21. A method according to claim 20, wherein step e4) lies in calculating at the card level the transform by the first cryptographic function of the keyword as the first operand, and of the value bits and of the signature bits as the second operand in series.

22. A method according to claim 14 wherein, in the event that the value bits are used up, wherein it comprises the following steps:

a) setting to zero the identification bits, the value bits and the signature bits before the reloading;

b) incrementing a reloading counter; and

c) reloading the new identification bits, the value bits and the signature bits into the card.

23. A method according to claim 14, wherein the value bits are encoded by a third cryptographic function specific to the card.

24. A method according to claim 23 wherein, in the event that the value bits are used up, wherein it comprises the following steps:

a) setting the identification bits and the value bits to zero before the reloading,

b) incrementing a reloading counter; and

c) reloading the identification bits and the value bits after the reloading.