High speed image processing computer

• US 5,129,060 A
• Filed: 01/24/1989
• Issued: 07/07/1992
• Est. Priority Date: 09/14/1987
• Status: Expired due to Term

• Current Assignee: GDE Systems, Inc. (The O'Gara Group, Inc.)
• Original Assignee: Visual Information Technologies Incorporated
• Inventors: Dipert, Dwight D., Thompson, Jay A., Corry, Michael K., Fontaine, James A., Stoner, David T., Norsworthy, John P., Pfeiffer, David M.
• Primary Examiner(s): Herndon, Heather R.
• Application Number:
  US07/301,373
• Time in Patent Office: 1,260 Days
• Field of Search: 364/518, 364/521, 364/200 MS File, 364/900 MS File, 340/721, 340/723, 340/798-800, 365/230
• US Class Current: 345/563
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 5/015 having at least two separately controlled shifting levels, e.g. using shifting matrices G06F5/012 takes precedence
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/49947 Rounding
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) assocated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). Mask data is generated by a mask processor coupled to the image algorithm processor (66) for masking one or more pixels in a multi-pixel word and further for masking individual bits within said pixels.

Claims

1. An image processing system, comprising:

an image memory for storing pixel data;

an address generator for generating addresses for accessing said image memory;

a data processor for processing said pixel data associated with said generated addresses;

a mask processor associated with said address generator for generating mask data responsive to said generated addresses; and

a bus connected between said address generator and said data processor for passing mask information therebetween.

2. The image processing system of claim 1, further including a plurality of data processors, each coupled together by said mask bus.

3. The image processing system of claim 2, wherein said mask comprises a multiconductor bus connected to each said data processor so as to achieve a wired arithmetic logic function.

4. The image processing system of claim 3, wherein each said data processor is connected together by said mask bus by a wired AND function.

5. The image processing system of claim 3, wherein said address generator is connected to said mask bus to provide a wired arithmetic function.

6. The image processing system of claim 2, wherein said mask processor comprises a first mask processor and further comprising a second mask processor coupled to said data processor for processing mask data generated by said first mask processor.

7. The image processing system of claim 6, further including circuitry in each said data processor for receiving mask information from said bus, and for storing said mask information to a register associated therewith.

8. The image processing system of claim 6 wherein said second mask processor is operable to communicate said generated mask data to others of said data processors.

9. The image processing system of claim 1, wherein said mask processor includes means for generating a word indicating pixels to be masked and a word indicating which bits in said pixels are to be masked.

10. The image processing system of claim 9, further including an expander for generating mask information for associating said bit word mask information with each said pixel to be masked as indicated by said pixel mask word.

11. An image processing system, comprising:

an image memory for storing pixel data;

circuitry for simultaneously writing plural pixels of data in said memory;

an address generator for generating addresses for accessing said image memory;

a data processor for processing said pixel data associated with said generated addresses; and

a mask processor coupled to said address generator for generating mask data responsive to said generated addresses, said mask data operable to prevent desired pixels from being written into said memory during write operations thereto.

12. The image processing system of claim 11, wherein said mask processor is operable to generate mask data identifying bits within ones of said pixels which should not be written into memory during said write operations.

13. A method of processing image data comprising the steps of:

storing the image data in an image memory;

generating addresses for accessing the image memory with an address generator;

processing the image data associated with the generated addresses with a data processor;

generating mask data responsive to the generated addresses; and

passing the mask information between the address generator and the data processor.

14. The method of claim 13 wherein said processing step comprises the step of processing image data associated with the generated addresses using a plurality of data processors, each data processor operable to pass mask information therebetween.

15. The method of claim 13 and further including the step of storing the mask information in a memory associated with the data processor.

16. The method of processing pixel data comprising the steps of:

simultaneously writing plural pixels in said memory;

generating addresses for accessing the image memory;

processing pixel data associated with the generated addresses;

generating mask data responsive to said generated addresses; and

preventing pixel data associated with the generated mask data from being written into the image memory during write operations thereto.

17. The method of claim 16 wherein said step of generating mask data comprises the step of generating mask data for identifying bits within ones of the pixels which should not be written into memory during the write operations.