VMEbus-UCDP interface module
First Claim
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1. An interface module (10) for exchanging electronic signals between a bus interface (VMEbus) (30) and an external channel (40), comprising:
- interface means (50) responsive to VMEbus address signals and operative to activate a plurality of SELECT signals;
input buffer means (80) enabled by a particular one of said SELECT signals and incremented by input data channel ready (IDR) and input data clamp (IDC) signals to store parallel bits of data-words received sequentially from said channel, and then to activate an input transfer complete (ITC) signal from indicating an input transfer complete condition, and then responsive to VMEbus address signals to transfer stored data-words to said VMEbus;
interrupt control means (110) responsive to another one of said SELECT signals and to signals indicating module and channel conditions to activate appropriate interrupt signals to said VMEbus;
output buffer means (130) responsive to still another one of said SELECT signals and to VMEbus address signals to store parallel-bit data-words from said VMEbus, and then responsive to module output data ready (ODR) and output data clamp (ODC) signals to transfer stored data-words sequentially to said channel, and then to activate an OTC signal for indicating an output transfer complete condition; and
timing signal generator means (150) responsive to an external channel output buffer ready (OBR) signal input to said interface means (50) and operative to generate a SEND signal to activate module ready ODR and clamp ODC signal lines for timing data-word transmissions by said output buffer means and receptions by said external channel.
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Abstract
An interface module for coupling a VMEbus channel to a Universal Common Data Point channel and exchanging data signals in either direction. The module responds to protocol handshake signals from the originating channel, accepts a multi-word message-block, and provides handshake signals to notify the destination channel of message to be delivered. The module then transfers the message-block to the destination channel.
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Citations
7 Claims
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1. An interface module (10) for exchanging electronic signals between a bus interface (VMEbus) (30) and an external channel (40), comprising:
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interface means (50) responsive to VMEbus address signals and operative to activate a plurality of SELECT signals; input buffer means (80) enabled by a particular one of said SELECT signals and incremented by input data channel ready (IDR) and input data clamp (IDC) signals to store parallel bits of data-words received sequentially from said channel, and then to activate an input transfer complete (ITC) signal from indicating an input transfer complete condition, and then responsive to VMEbus address signals to transfer stored data-words to said VMEbus; interrupt control means (110) responsive to another one of said SELECT signals and to signals indicating module and channel conditions to activate appropriate interrupt signals to said VMEbus; output buffer means (130) responsive to still another one of said SELECT signals and to VMEbus address signals to store parallel-bit data-words from said VMEbus, and then responsive to module output data ready (ODR) and output data clamp (ODC) signals to transfer stored data-words sequentially to said channel, and then to activate an OTC signal for indicating an output transfer complete condition; and timing signal generator means (150) responsive to an external channel output buffer ready (OBR) signal input to said interface means (50) and operative to generate a SEND signal to activate module ready ODR and clamp ODC signal lines for timing data-word transmissions by said output buffer means and receptions by said external channel. - View Dependent Claims (2, 3, 4, 5)
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6. A module (10) for a VMEbus (30) interface to an external channel (40), said module comprising:
- input buffer means (80) including
an address counter (U23) responsive to an input transfer complete condition to activate an input transfer complete (ITC) signal line, and responsive to module RESET or channel input data ready (IDR) signals to clear the ITC and address signal output lines of the counter; an address multiplexer (U15, U16) switched by a cleared ITC signal to select buffer address signal lines form said counter; a memory (U17, U18) addressed by signal lines selected by said multiplexer; a receive register (U19, U20) for receiving parallel 16-bit data-words from said channel; wherein channel input data clamp (IDC) signals synchronously strobe si register (U19, U20), said multiplexer (U15, U16) and said counter (U23) and in response, in each IDC signal cycle, simultaneously a channel data-word is latched n by said receive register, the previously-latched data-word is read sequentially into said memory, and said address counter is incremented to repeat the cycle until reaching a specified total message word number and thereby reactivating the ITC signal output line, which switches said multiplexer to select buffer address signal lines from said VMEbus; and a transmit register (U21, U22) through which, as a result of VMEbus signals addressing said memory, stored data-words are transferred to data lines of said VMEbus, unless said buffer means (80) is concurrently read and written, which activates an overrun (OVRRN) error signal. - View Dependent Claims (7)
- input buffer means (80) including
Specification