Post fabrication processing of semiconductor chips

• US 5,130,275 A
• Filed: 07/02/1990
• Issued: 07/14/1992
• Est. Priority Date: 07/02/1990
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Dion, John B.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): DANG, TRUNG Q
• Application Number:
  US07/547,652
• Time in Patent Office: 743 Days
• Field of Search: 437/183, 437/190, 437/192, 437/246, 437/944, 228/180.2, 228/188, 228/254
• US Class Current: 438/614
• CPC Class Codes: C23F 1/38 for etching refractory metals
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11903 using different masks
• CPC Class Codes: H01L 2224/13019 at the bonding interface of the bump connector, i.e. on the surface of the bump connector
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A method for processing semiconductor chips which deters the formation of "tin whiskers" and which removes excess substrate material from the passive side of a semiconductor device is presented. The deterrence of tin whiskers is accomplished by controlling the size of the bead of flowable metal on the conductive bump. The removal of excess material from the passive side of the semiconductor device is accomplished by chemical reaction after the formation of the conductive bump.

Claims

1. A method for forming a pattern of electrically conductive pads on a semiconductor device, said semiconductor device having an active side and a passive side, comprising the steps of:

creating a plurality of bumps on said active side in accordance with said pattern, said bumps having edges, said edges being separated from the adjacent edge of the adjacent bump by a nominal distance, and said bumps having a nominal width;

patterning on said active side a mask, said mask having openings above said bumps, each of said openings having walls, said walls being separated by a nominal width, and said walls being separated from the adjacent wall of the adjacent opening by a nominal distance, said nominal width of separation of said walls being less than said nominal width of said bumps, and said nominal distance separating said bumps being less than said nominal distance separating said adjacent walls of adjacent openings;

depositing into said openings a flowable alloy, said flowable alloy contacting said walls and completely filling the width between said walls;

completely removing said mask.

2. A method for forming a pattern of electrically conductive pads on a semiconductor device as in claim 1, said mask being composed of photoresist.

3. A method for forming a pattern of electrically conductive pads on a semiconductor device as in claim 1, said nominal width of separation of said walls being at least 15% narrower than said nominal width of said bumps.

4. A method for forming a pattern of electrically conductive pads on a semiconductor device as in claim 1, said flowable alloy containing tin.

5. A method for forming a pattern electrically conductive pads on a semiconductor device as in claim 1, said bumps containing gold or copper.

6. A method for forming a pattern of electrically conductive pads on a semiconductor device as in claim 1, said mask opening being greater than 4 microns thick.

15. A method for forming a pattern of electrically conductive pads on a semiconductor device as in claim 1, wherein said depositing of said flowable alloy is by electrodeposition.

16. The method for forming a pattern of electrically conductive pads on a semiconductor device as in claim 1, said semiconductor pads having interconnect pads, wherein said bumps are placed above said interconnect pads and said bumps are separated from said interconnect pads by a lamina of barrier metal, said barrier metal lamina being formed by

depositing a barrier metal layer on said semiconductor device prior to creating said bumps;

and

subsequent to creating said bumps, removing the portion of said barrier metal layer not lying under said bumps.

17. The method for forming a pattern of electrically conductive pads on a semiconductor device as in claim 16, wherein removing the portion of said barrier layer not lying under said bumps includes the step of exposing said portion of said barrier layer to a solution with a pH of between approximately 9 and approximately 11.

18. The method for forming a pattern of electrically conductive pads on a semiconductor device as in claim 16, said solution containing a perioxide.

19. The method for forming a pattern of electrically conductive pads on a semiconductor device as in claim 18, said perioxide being ammonium peroxide, and said solution further containing oxidized ammonium persulfate.

20. The method for forming a pattern of electrically conductive pads on a semiconductor device as in claim 19, said oxidized ammonium persulfate being approximately 7% of the solution by weight.

21. The method for forming a pattern of electrically conductive pads on a semiconductor device as in claim 1, said semiconductor device having an active side and a passive side, said active side having interconnect pads, wherein creating said bumps includes the steps of:

patterning on said active side a photoresist layer, said photoresist layer having openings above said interconnect pads;

depositing bump material into said openings;

exposing said semiconductor device to a chemical solution which removes material from the surface of said semiconductor device;

wherein said photoresist layer and said bump material prevent said chemical from removing material from the active side of said semiconductor device.

22. The method for forming a pattern of electrically conductive pads on a semiconductor device as in claim 21, wherein said chemical solution contains hydrofluoric acid.

23. The method for forming a pattern of electrically conductive pads as in claim 22, wherein said chemical solution further contains nitric acid.

7. A method for forming a row of aligned electrically conductive pads on a semiconductor device comprising the steps of:

creating a plurality of electrically conductive bumps in accordance with the desired pattern of said row, said bumps having edges, said bumps having a nominal width along the axis of alignment of the conductive pads, and said bump edges having a nominal distance between the adjacent bump edges of adjacent bumps;

patterning on said bumps a mask, said mask having openings above said bumps, said openings having edges, said openings having a nominal width along the axis of alignment of the conductive pads, and said opening edges having a nominal distance between the adjacent edges of adjacent openings, wherein said nominal distance between said opening edges is greater than said nominal distance between said bumps;

depositing into said openings a flowable alloy and completely removing said mask.

8. A method for physically and electrically connecting at least one TAB lead with a bump on a semiconductor device comprising the steps of:

creating a plurality of bumps, said bumps having edges, said edges being separated from the adjacent edge of the adjacent bump by a nominal distance, and said bumps having a nominal width;

patterning on said bumps a mask, said mask having openings above said bumps, each of said openings having walls, said walls being separated by a nominal width, and said walls being separated from the adjacent wall of the adjacent opening by a nominal distance, said nominal width of separation of said walls being less than said nominal width of said bumps, and said nominal distance separating said bumps being lesser than said nominal distance separating said adjacent walls of adjacent openings;

depositing into said openings a bead of a flowable alloy said flowable alloy contacting said walls and completely filling the width between said walls;

completely removing said mask;

placing said TAB lead on said flowable alloy on one of said bumps;

causing said flowable alloy to flow and causing said flowable alloy to solidify.

9. A method for physically and electrically connecting a semiconductor device and leads on TAB tape as in claim 8, said nominal width of separation - of said walls aid being at least 15% narrower than said nominal width of said bumps.

10. A method for physically and electrically connecting a semiconductor device and leads on TAB tape as in claim 8, said flowable alloy containing tin.

11. A method for physically and electrically connecting a semiconductor device and leads on TAB tape as in claim 10, said bump containing gold or copper.

12. A method for physically and electrically connecting a semiconductor device and leads on TAB tape as in claim 8, said lead being at least as wide as said nominal width of said bead of flowable alloy.

13. A method for physically and electrically connecting a semiconductor device and leads on TAB tape as in claim 8, said bump containing gold or copper.

14. A method for physically and electrically connecting a semiconductor device and leads on TAB tape as in claim 8, said mask opening being greater than 4 microns thick.