Integrated circuit self-testing device and method

• US 5,130,644 A
• Filed: 01/29/1991
• Issued: 07/14/1992
• Est. Priority Date: 11/23/1988
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ott, Granville E.
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): BURNS, WILLIAM
• Application Number:
  US07/648,329
• Time in Patent Office: 532 Days
• Field of Search: 324/158 P, 324/158 F, 324/501, 324/158 D, 324/158 R, 437/8, 250/341
• US Class Current: 324/750.3
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]

Abstract

A semiconductor wafer (26) may have all the integrated circuits (36) formed thereon simultaneously self-tested by the addition of a power circuit, a ground circuit and clock circuit. Lead lines are formed during metallization of the integrated circuits (36) on the wafer (26). The lead lines are interconnected to the integrated circuits (36) to form a power input, a ground input and a clock input on each integrated circuit (36). A test head (28) having a power probe (44), a ground probe (46) and clock probe (48) is attached to the power, ground and clock circuits on the semiconductor wafer (36). The integrated circuits (36) are simultaneously tested by the test head (28), and failed circuits are identified by an infrared detector (42).

Claims

1. A method for forming a semiconductor wafer for simultaneously self testing integrated circuits thereon, comprising the steps of:

interconnecting a power circuit formed in a first metallization layer to a power input on the integrated circuits;

interconnecting a ground circuit formed in said first metallization layer to a ground input on the integrated circuits;

interconnecting a clock circuit formed in a second metallization layer to a clock input on the integrated circuits to allow the integrated circuits to be simultaneously tested; and

interconnecting an infrared indicating circuit to optically indicate a test pass/fail condition for each integrated circuit.

2. The method of claim 1, wherein the step of interconnecting said power circuit comprises the steps of:

forming a plurality of lead lines between the integrated circuits during a metallization of the wafer; and

connecting said lines to form a bus for power input.

3. The method of claim 1, wherein the step of interconnecting said ground circuit comprises the steps of:

forming a plurality of lead lines between the integrated circuits during a metallization of the wafer; and

connecting said lines to form a bus for ground input.

4. The method of claim 1, wherein the step of interconnecting said clock circuit comprises the steps of:

forming a plurality of lead lines between the integrated circuits during a metallization of the wafer; and

connecting said lines to form a bus for clock input.

5. The method of claim 1, further comprising the step of connecting a plurality of capacitors between said power circuit and said ground circuit to avoid excessive power and ground noise.

6. The method of claim 1, further including the step of connecting an external source to said circuits to provide power, ground and clock.

7. The method of claim 1 and further comprising:

testing the integrated circuits by applying selected voltages to said power, ground and clock circuits; and

detecting selected characteristics of the integrated circuits in response to said selected voltages using said infrared indicating circuit.

8. A method for simultaneously self-testing a plurality of integrated circuits on a semiconductor wafer, comprising the steps of:

forming a plurality of first lead lines on the wafer interconnected to at least one power input on the integrated circuits;

forming a plurality of second lead lines on the wafer interconnected to at least one ground input on the integrated circuits, wherein said pluralities of first and second lead lines comprise a first metallization layer;

forming a plurality of third lead lines on the wafer interconnected to a clock input on the integrated circuits, wherein said plurality of third lead lines comprise a second metallization layer;

forming an insulator layer between said first and second metallization layers;

providing power, ground and clock with a test head to said first, second and third lead lines to simultaneously self-test the integrated circuits on the wafer; and

providing a detecting circuit to optically detect a test pass/fail condition for each integrated circuit.

9. The method of claim 8, wherein the steps of forming lead lines comprise:

metallizing the wafer;

patterning said lines; and

etching said patterned lines.

10. A method for simultaneously self-testing a plurality of integrated circuits on a semiconductor wafer, comprising:

a plurality of first lead lines formed on the wafer and interconnected to at least one power input on the integrated circuits;

a plurality of second lead lines formed on the wafer and interconnected to at least one ground input on the integrated circuits;

a plurality of third lead lines formed on the wafer and interconnected to a clock input on the integrated circuits, wherein said first and second lead lines comprise a second metallization layer, and said third lead line comprises a second metallization layer separated from said first metallization layer by an insulator; and

a test head for providing power, ground and clock to said first, second and third lead lines to simultaneously self-test the integrated circuits on the wafer;

wherein said test head further comprises an infrared detector.

11. The apparatus of claim 10, wherein each of said plurality of first lead lines are connected together to form a wafer power input bus.

12. The apparatus of claim 10, wherein each of said plurality of second lead lines are connected together to form a wafer power input bus.

13. The apparatus of claim 10, wherein each of said plurality of third lead lines are connected together to form a wafer power input bus.

14. The apparatus of claim 10, further including a plurality of capacitors interconnected between said first lines and said second lines to avoid excessive power and ground noise.

15. The apparatus of claim 10, wherein said test head comprises:

a platform;

a power probe on said platform;

a ground probe on said platform; and

a clock probe on said platform to allow said test head to be positioned over the wafer to test circuits thereon.

16. The apparatus of claim 15, further comprising an infrared lens interconnected to said infrared detector for observing the circuits during testing to locate failed circuits.

17. The apparatus of claim 16, further including a wide-angle lens to allow the plurality of the integrated circuits to be viewed simultaneously.

18. The apparatus of claim 16, further including a scanner device to sequentially view the plurality of integrated circuits.

19. The apparatus of claim 15, further including a plurality of capacitor probes capable of connection between said plurality of first lead lines and said plurality of second lead lines to avoid excessive power and ground noise.

20. The apparatus of claim 10, wherein said test head further includes a dye marker to mark failed circuits.

21. The apparatus of claim 16, further comprising a resistor on each of the circuits to indicate a test pass/fail condition.

22. A semiconductor wafer for enabling self-testing of integrated circuits thereon, comprising:

a power circuit interconnected to a power input on the integrated circuits;

a first probe for supplying power to said power circuit;

a ground circuit interconnected to a ground input on the integrated circuits;

a second probe for supplying power to said ground circuit;

a clock circuit interconnected to a clock input on the integrated circuits being operable to allow the integrated circuits to be simultaneously tested;

a third probe for supplying power to said clock circuit;

a plurality of capacitor probes insertable between said power circuit and said ground circuit to avoid excessive power and ground noise;

a means for holding said first, second, third, and capacitor probes to allow placement over a wafer to be tested; and

an indicating circuit, wherein said circuit optically indicates a test pass/fail condition for each integrated circuit.

23. The wafer of claim 22 wherein said power circuit comprises:

a plurality of lead lines formed on the wafer during a metallization of the wafer extending between the integrated circuits; and

a bus for allowing said lines to be powered by a single, external source.

24. The wafer of claim 22 wherein said ground circuit comprises:

a plurality of lead lines formed on the wafer during a metallization of the wafer extending between the integrated circuits; and

a bus for allowing said lines to be grounded by a single, external source.

25. The wafer of claim 22 wherein said clock circuit comprises:

a plurality of lead lines formed on the wafer during a metallization of the wafer extending between the integrated circuits; and

a bus for allowing said lines to be provided with clock data from a single, external source.

26. The wafer of claim 22, further including a plurality of capacitors connected between said power circuit and said ground circuit to avoid excessive power and ground noise.

27. The wafer of claim 22 wherein said means for holding comprises a platform.

28. The wafer of claim 27, wherein said platform further includes means for marking failed integrated circuits.