Integrated circuit self-testing device and method
First Claim
1. A method for forming a semiconductor wafer for simultaneously self testing integrated circuits thereon, comprising the steps of:
- interconnecting a power circuit formed in a first metallization layer to a power input on the integrated circuits;
interconnecting a ground circuit formed in said first metallization layer to a ground input on the integrated circuits;
interconnecting a clock circuit formed in a second metallization layer to a clock input on the integrated circuits to allow the integrated circuits to be simultaneously tested; and
interconnecting an infrared indicating circuit to optically indicate a test pass/fail condition for each integrated circuit.
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Accused Products
Abstract
A semiconductor wafer (26) may have all the integrated circuits (36) formed thereon simultaneously self-tested by the addition of a power circuit, a ground circuit and clock circuit. Lead lines are formed during metallization of the integrated circuits (36) on the wafer (26). The lead lines are interconnected to the integrated circuits (36) to form a power input, a ground input and a clock input on each integrated circuit (36). A test head (28) having a power probe (44), a ground probe (46) and clock probe (48) is attached to the power, ground and clock circuits on the semiconductor wafer (36). The integrated circuits (36) are simultaneously tested by the test head (28), and failed circuits are identified by an infrared detector (42).
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Citations
28 Claims
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1. A method for forming a semiconductor wafer for simultaneously self testing integrated circuits thereon, comprising the steps of:
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interconnecting a power circuit formed in a first metallization layer to a power input on the integrated circuits; interconnecting a ground circuit formed in said first metallization layer to a ground input on the integrated circuits; interconnecting a clock circuit formed in a second metallization layer to a clock input on the integrated circuits to allow the integrated circuits to be simultaneously tested; and interconnecting an infrared indicating circuit to optically indicate a test pass/fail condition for each integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for simultaneously self-testing a plurality of integrated circuits on a semiconductor wafer, comprising the steps of:
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forming a plurality of first lead lines on the wafer interconnected to at least one power input on the integrated circuits; forming a plurality of second lead lines on the wafer interconnected to at least one ground input on the integrated circuits, wherein said pluralities of first and second lead lines comprise a first metallization layer; forming a plurality of third lead lines on the wafer interconnected to a clock input on the integrated circuits, wherein said plurality of third lead lines comprise a second metallization layer; forming an insulator layer between said first and second metallization layers; providing power, ground and clock with a test head to said first, second and third lead lines to simultaneously self-test the integrated circuits on the wafer; and providing a detecting circuit to optically detect a test pass/fail condition for each integrated circuit. - View Dependent Claims (9)
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10. A method for simultaneously self-testing a plurality of integrated circuits on a semiconductor wafer, comprising:
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a plurality of first lead lines formed on the wafer and interconnected to at least one power input on the integrated circuits; a plurality of second lead lines formed on the wafer and interconnected to at least one ground input on the integrated circuits; a plurality of third lead lines formed on the wafer and interconnected to a clock input on the integrated circuits, wherein said first and second lead lines comprise a second metallization layer, and said third lead line comprises a second metallization layer separated from said first metallization layer by an insulator; and a test head for providing power, ground and clock to said first, second and third lead lines to simultaneously self-test the integrated circuits on the wafer; wherein said test head further comprises an infrared detector. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A semiconductor wafer for enabling self-testing of integrated circuits thereon, comprising:
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a power circuit interconnected to a power input on the integrated circuits; a first probe for supplying power to said power circuit; a ground circuit interconnected to a ground input on the integrated circuits; a second probe for supplying power to said ground circuit; a clock circuit interconnected to a clock input on the integrated circuits being operable to allow the integrated circuits to be simultaneously tested; a third probe for supplying power to said clock circuit; a plurality of capacitor probes insertable between said power circuit and said ground circuit to avoid excessive power and ground noise; a means for holding said first, second, third, and capacitor probes to allow placement over a wafer to be tested; and an indicating circuit, wherein said circuit optically indicates a test pass/fail condition for each integrated circuit. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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Specification