Large fault tolerant packet switch particularly suited for asynchronous transfer mode (ATM) communication

• US 5,130,984 A
• Filed: 12/18/1990
• Issued: 07/14/1992
• Est. Priority Date: 12/18/1990
• Status: Expired due to Term

• Current Assignee: TTI Inventions A LLC (Intellectual Ventures LLC)
• Original Assignee: Bell Communications Research, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Cisneros, Arturo
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): HOM, SHICK C
• Application Number:
  US07/629,584
• Time in Patent Office: 574 Days
• Field of Search: 370/94.1, 370/85.2, 370/85.6, 370/60, 370/60.1, 370/61, 379/291, 379/292, 379/335, 340/825.85, 340/825.89
• US Class Current: 370/399
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/561 Star, e.g. cross-connect, concentrator, subscriber group equipment, remote electronics
• CPC Class Codes: H04L 2012/5627 Fault tolerance and recovery
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 49/108 using shared central buffer
• CPC Class Codes: H04L 49/153 ATM switching fabrics having parallel switch planes
• CPC Class Codes: H04L 49/1576 Crossbar or matrix
• CPC Class Codes: H04L 49/309 Header conversion, routing tables or routing tags
• CPC Class Codes: H04Q 11/0005 Switch and router aspects
• CPC Class Codes: H04Q 11/0066 Provisions for optical burst or packet networks
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections
• CPC Class Codes: H04Q 2011/0009 using wavelength filters
• CPC Class Codes: H04Q 2011/0015 using splitting combining
• CPC Class Codes: H04Q 2011/0018 using tunable transmitters or receivers
• CPC Class Codes: H04Q 2011/0039 Electrical control
• CPC Class Codes: H04Q 2011/0043 Fault tolerance
• CPC Class Codes: H04Q 2011/0052 Interconnection of switches

Abstract

Apparatus, and accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch (200), particularly suited for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing cross-points (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively). An ATM cell applied to an input port of an interface module contains a data field and a virtual channel identifier (VCI) field. The VCI is translated by the interface module into a new VCI, to identify an output of the virtual channel for the switch and appends to the cell an additional routing header which will be used strictly for internal use in routing the entire cell through the switch and which includes distinct first and second portions.

Claims

1. Apparatus for a packet switch comprising:

a plurality of input modules, wherein each of said input modules provides a plurality of input ports and a plurality of outputs and applies incoming packets from said input ports to said outputs in a first pre-defined fashion, each of said incoming packets having first and second distinct address portions and a data portion therein;

a plurality of output modules, wherein each of said output modules has a plurality of inputs and provides a plurality of output ports and applies in a second pre-defined fashion data portions of outgoing packets from said inputs to said output ports;

a plurality of cross-point switching circuits, wherein each of said switching circuits is connected to a corresponding output of each of said input modules and to a corresponding input to each of said output modules, wherein each of said switching circuits comprises;

means, responsive to the first address portion of each of the incoming packets applied over said corresponding output from any of said input modules, for establishing for said each incoming packet a route through said switching circuit and over said corresponding output to an addressed one of said output modules; and

wherein each of said output modules comprises means, responsive to the second address portion contained within a packet applied to said each output module by any of said switching circuits, for applying the data portion contained within said applied packet to an addressed one of the plurality of said output ports associated therewith.

2. The apparatus in claim 1 wherein the pluralities of input and output modules each respectively comprise "k" substantially identical input and output modules, with each of said input modules providing "n" of said input ports and "m" of said outputs and each of said output modules providing "m" of said inputs and "n" of said output ports, and the plurality of cross-point switching circuits comprises "m" separate substantially identical k-by-k cross-point switching circuits, where "n", "k" and "m" are pre-defined integer values.

3. The apparatus in claim 1 further comprising:

means, responsive to incoming ATM cells appearing on a user line, for prepending a predefined routing header to of said ATM cells so as to form an associated one of said incoming packets, wherein said routing header is formed of the first and second address portions and said each ATM cell is the data portion; and

means, connected to said prepending means, for applying said associated ones of the incoming packets produced thereby to a corresponding one of said input ports.

4. The apparatus in claim 3 wherein said prepending means further comprises means for translating a value of a virtual channel identifier field appearing in said incoming ATM cell to produce said first and second address portions therefor.

5. The apparatus in claim 2 wherein a packet period is formed of "m" successive intervals and the cross-point switching circuits are all operated on a time staggered basis with respect to each other such that each of said switching circuits commences routing a group of up to "k" of said incoming packets therethrough beginning at a time approximately one of said "m" intervals prior to a corresponding time at which a next successive one of said switching circuits commences routing a next successive group of up to "k" of said incoming packet therethrough, and

wherein each of said input modules comprises:

means for storing incoming packets in a queue on a first-in first-out basis;

means, connected to the plurality of input ports to said each input module and to said storing means, for successively reading every one of said input ports in a round-robin fashion during a packet period and writing a current one of said incoming packets appearing on each of said input ports into successive locations in said queue; and

means, connected to said storing means and to said "m" outputs emanating from said each input module, for reading an incoming packet situated at a head of the queue in said storing means and for applying, during each one of said "m" successive intervals, said incoming packet so read to a next successive one of said "m" outputs in round-robin fashion from said each input module, such that during the interval one of the switching circuits that is connected to said next successive output emanating from each of said input modules receives a group of up to "k" essentially simultaneously occurring ones of said incoming packets from all of said input modules.

6. The apparatus in claim 5 wherein said apparatus further comprises means, connected to all the input modules, for resolving output contention among all the incoming packets then situated at the head of the queues within all the "k" input modules;

and said reading and applying means within each of said "k" input modules further comprises;

means for sending the first address portion of an incoming packet situated at the head of the queue within said each input module to said contention resolving means; and

means, responsive to a control signal generated by said contention resolving means, for providing the incoming packet situated at the head of the queue within said each input module to said next successive output only in the event no contention has occurred or output contention has been resolved in favor of said each input module.

7. The apparatus in claim 6 wherein said contention resolving means resolves contention during each of said "m" intervals for a corresponding one of said groups of up to "k" incoming packets, wherein each of the said groups is formed of packets then currently situated at a head of each queue within every one of said "k" input modules.

8. The apparatus in claim 5 wherein each of said output modules comprises:

"n" first-in first-out queues;

means, connected to the plurality of inputs to said each output module, for reading an outgoing packet appearing on each of said outputs in a round-robin fashion during a packet period;

means, responsive to said reading means and connected to said "n" queues, for examining the second address portion in each of the outgoing packets appearing on each of said inputs, and for depositing, in response to said second address portion so read, the data portion of said each outgoing packet in an end of a correspondingly addressed one of said queues; and

means, connected to said "n" queues and to the output ports emanating from said each output module, for successively reading during a packet period the outgoing packets situated at the head of each of the "n" queues in a round-robin fashion and for applying during, said packet period, each of the outgoing packets so read to a corresponding one of said output ports.

9. The apparatus in claim 5 wherein each of said cross-point switching circuits has "k" inputs and "k" outputs and comprises:

a plurality of switching elements, each of which can assume either an open or closed state and all of which are collectively interconnected in a matrix arrangement, said matrix being connected to the corresponding output from each of said input modules and to the corresponding input to each of said output modules;

means, connected to all of said switching elements and responsive to the first address portions contained within the group of up to "k" incoming packets applied to said switching circuit over said corresponding output from all of said input modules, for defining a next successive state of all of the switching elements needed to properly route the group of "k" incoming packets through said each circuit so as to establish a new configuration thereof; and

means, connected to the switching elements and responsive to a strobe signal, for setting the state of all of said switching elements as defined by the new configuration.

10. The apparatus in claim 9 wherein said defining means comprises means for establishing the new configuration of said each switching circuit for a corresponding group of incoming packets in advance of the application of the corresponding group as input to said each switching circuit.

11. The apparatus in claim 10 wherein the new configuration is set one packet period in advance of the corresponding group of incoming packets that is to be applied as input to said each switching circuit.

12. The apparatus in claim 9 wherein said defining means comprises means for establishing the new configuration of said each switching circuit for a corresponding group of said incoming packets that are currently being applied as input to said each switching circuit.

13. Apparatus for a packet switch comprising:

"k" substantially identical input modules, wherein each of said input modules provides "n" separate input ports and "m" separate outputs and applies incoming packets from said input ports to said outputs in a first pre-defined fashion, each of said incoming packets having first and second distinct address portions and a data portion therein;

"k" substantially identical output modules, wherein each of said output modules has "m" separate inputs and provides "n" separate output ports and applies in a second pre-defined fashion data portions of outgoing packets from said inputs to said output ports;

"m" substantially identical k-by-k cross-point switching circuits (where "k", "m" and "n" are all pre-defined integer values), wherein each of said switching circuits is connected to a corresponding one of the "m" outputs of each of said input modules, all the corresponding outputs having the same numerical ranking, and to a corresponding input to each of said output modules, all of the corresponding inputs having the same numerical ranking, wherein each of said "m" switching circuits comprises;

means, responsive to the first address portion of each of the incoming packets applied over said corresponding output from any of said "k" input modules, for establishing for said each incoming packet a route through said each switching circuit and over said corresponding output to an addressed one of said "k" output modules; and

wherein each of said "k" output modules comprises means, responsive to, the second address portion contained within a packet applied to said each output module by any of said "m" switching circuits, for applying the data portion contained within said applied packet to an addressed one of the "n" output ports associated therewith.

14. The apparatus in claim 13 further comprising:

means, responsive to incoming ATM cells appearing on a user line, for prepending, a predefined routing header to each of said ATM cells so as to form an associated one of said incoming packets, wherein said routing header is formed of the first and second address portions and said each ATM cell is the data portion; and

means, connected to said prepending means, for applying said associated ones of the incoming packets produced thereby to a corresponding one of said input ports.

15. The apparatus in claim 14 wherein each of said input modules comprises:

means for storing incoming packets in a queue on a first-in first-out basis;

means, connected to the "n" input ports to said each input module and to said storing means, for successively reading every one of said input ports in a round-robin fashion during a packet period and writing a current one of said incoming packets appearing on each of said input ports into successive locations in said queue; and

means, connected to said storing means and to said "m" outputs emanating from said each input module, for reading an incoming packet situated at a head of the queue in said storing means and for applying, during each one of said "m" successive intervals, said incoming packet so read to a next successive one of said "m" outputs in round-robin fashion from said each input module, such that during the interval one of the switching circuits that is connected to said next successive output emanating from each of said input modules receives a group of up to "k" essentially simultaneously occurring ones of said incoming packets from all of said input modules.

16. The apparatus in claim 15 wherein said apparatus further comprises means, connected to all the input modules, for resolving output contention among all the incoming packets then situated at the head of the queues within all the "k" input modules;

and said reading and applying means within each of said "k" input modules further comprises;

means for sending the first address portion of an incoming packet situated at the head of the queue within said each input module to said contention resolving means; and

means, responsive to a control signal generated by said contention resolving means, for providing the incoming packet situated at the head of the queue within said each input module to said next successive output only in the event no contention has occurred or output contention has been resolved in favor of said each input module.

17. The apparatus in claim 16 wherein each of said output modules comprises:

"n" first-in first-out queues;

means, connected to the "m" inputs to said each output module, for reading an outgoing packet appearing on each of said outputs in a round-robin fashion during a packet period;

means, responsive to said reading means and connected to said "n" queues, for examining the second address portion in each of the outgoing packets appearing on each of said inputs, and for depositing, in response to said second address portion so read, the data portion of said each outgoing packet in an end of a correspondingly addressed one of said queues; and

means, connected to said "n" queues and to the output ports emanating from said each output module, for successively reading during a packet period the outgoing packets situated at the head of each of the "n" queues in a round-robin fashion and for applying during, said packet period, each of the outgoing packets so read to a corresponding one of said output ports.

18. The apparatus in claim 16 wherein each of said cross-point switching circuits has "k" inputs and "k" outputs and comprises:

a plurality of switching elements, each of which can assume either an open or closed state and all of which are collectively interconnected in a matrix arrangement, said matrix being connected to the corresponding output from each of said input modules and to the corresponding input to each of said output modules;

means, connected to all of said switching elements and responsive to the first address portions contained within the group of up to "k" incoming packets applied to said switching circuit over said corresponding output from all of said input modules, for defining a next successive state of all of the switching elements needed to properly route the group of "k" incoming packets through said each circuit so as to establish a new configuration thereof; and

means, connected to the switching elements and responsive to a strobe signal, for setting the state of all of said switching elements as defined by the new configuration.

19. The apparatus in claim 18 wherein said defining means comprises means for establishing the new configuration of said each switching circuit for a corresponding group of incoming packets in advance of the application of the corresponding group as input to said each switching circuit.

20. The apparatus in claim 18 wherein said defining means comprises means for establishing the new configuration of said each switching circuit for a corresponding group of said incoming packets that are currently being applied as input to said each switching circuit.

21. In a packet switch having a plurality of input modules each providing a plurality of input ports and having a plurality of outputs, a plurality of output modules each having a plurality of inputs and providing a plurality of output ports, and a plurality of cross-point switching circuits each being connected to a corresponding output of each of said input modules and to a corresponding input to each of said output modules, and wherein each of said incoming packets has first and second distinct address portions and a data portion therein, a method for routing packets through said switch comprising the steps of:

in each input module, applying incoming packets from said input ports thereto to said outputs thereof in a first pre-defined fashion;

in each output module, applying, in a second pre-defined fashion, data portions of outgoing packets from said inputs thereto to said output ports therefrom;

in each cross-point switching circuit;

establishing, in response to the first address portion of each of the incoming packets applied over said corresponding output from any of said input modules, a route for said each incoming packet through said switching circuit and over said corresponding output to an addressed one of said output modules; and

routing a of said each incoming packet over said route as a corresponding one of said outgoing packets to said addressed output module; and

wherein said method further comprises the step, within each of said output modules, of applying, in response to the second address portion contained within said one outgoing packet applied to said each output module by any of said cross-point switching circuits, the data portion contained within said one outgoing packet to an addressed one of the plurality of said output ports associated therewith.

22. The method in claim 21 wherein the pluralities of input and output modules each respectively comprise "k" substantially identical input and output modules, with each of said input modules providing "n" of said input ports and "m" of said outputs and each of said output modules providing "m" of said inputs and "n" of said output ports, and the plurality of cross-point switching circuits comprises "m" separate substantially identical k-by-k cross-point switching circuits, where "n", "k" and "m" are pre-defined integer values.

23. The method in claim 22 wherein the corresponding output has an identical numerical ranking across all the input modules and the corresponding input has an identical numerical ranking across all the output modules.

24. The method in claim 22 further comprising the steps of:

prepending, in response to incoming ATM cells appearing on a user line, a predefined routing header to each of said ATM cells so as to form an associated one of said incoming packets, wherein said routing header is formed of the first and second address portions and said each ATM cell is the data portion; and

applying said associated ones of the incoming packets produced thereby to a corresponding one of said input ports.

25. The method in claim 24 wherein said prepending step further comprises the step of translating a value of a virtual channel identifier field appearing in said incoming ATM cell to produce said first and second address portions therefor.

26. The method in claim 25 wherein a packet period is formed of "m" successive intervals and said method further comprises the step of operating all the cross-point switching circuits on a time staggered basis with respect to each other such that each of said switching circuits commences routing a group of up to "k" of said incoming packets therethrough beginning at a time approximately one of said "m" intervals prior to a corresponding time at which a next successive one of said switching circuits commences routing a next successive group of up to "k" of said incoming packets therethrough.

27. The method in claim 26 wherein, in each of said input modules, said method further comprises the steps of:

storing incoming packets in a queue on a first-in first-out basis;

successively reading every one of said input ports in a round-robin fashion during a packet period and writing a current one of said incoming packets appearing on each of said input ports into successive locations in said queue; and

reading an incoming packet situated at a head of the queue in said storing step and applying, during each one of said "m" successive intervals, said incoming packet so read to a next successive one of said "m" outputs in round-robin fashion from said each input module, such that during the interval one of the switching circuits that is connected to said next successive output emanating from each of said input modules receives a group of up to "k" essentially simultaneously occurring ones of said incoming packets from all of said input modules.

28. The method in claim 27 wherein said method further comprises the step of resolving output contention among all the incoming packets then situated at the head of the queues within all the "k" input modules;

and in each of said "k" input modules said reading and applying step comprises the steps of;

sending the first address portion of an incoming packet situated at the head of the queue within said each input module to said contention resolving step; and

providing, in response to a control signal generated by said contention resolving step, the incoming packet situated at the head of the queue within said each input module to said next successive output only in the event no contention has occurred or output contention has been resolved in favor of said each input module.

29. The method in claim 28 wherein said contention resolving step further comprises the step of resolving contention during each of said "m" intervals for a corresponding one of said groups of up to "k" incoming packets, wherein each of the said groups is formed of packets then currently situated at a head of each queue within every one of said "k" input modules.

30. The method in claim 26 wherein, in each of said output modules, said method further comprises the steps of:

reading an outgoing packet appearing on each of said outputs in a round-robin fashion during a packet period;

examining, in response to said outgoing packet reading step, the second address portion in each of the outgoing packets appearing on each of said inputs, and depositing, in response to said second address portion so read, the data portion of said each outgoing packet in an end of a correspondingly addressed one of "n" first-in first-out queues; and

successively reading during a packet period the outgoing packets situated at the head of each of the "n" queues in a round-robin fashion and applying during, said packet period, each of the outgoing packets so read to a corresponding one of said output ports.

31. The method in claim 26 wherein each of said cross-point switching circuits has "k" inputs and "k" outputs and wherein, in each of said switching circuits, said method further comprises the steps of:

defining, in response to the first address portions contained within the group of up to "k" incoming packets applied to said switching circuit over said corresponding output from all of said input modules, a next successive state of all switching elements contained within said each switching circuit needed to properly route the group of "k" incoming packets through said each circuit so as to establish a new configuration thereof; and

setting, in response to a strobe signal, the state of all of said switching elements as defined by the new configuration.

32. The method in claim 31 wherein said defining step comprises the step of establishing the new configuration of said each switching circuit for a corresponding group of incoming packets in advance of the application of the corresponding group as input to said each switching circuit.

33. The method in claim 32 wherein the new configuration is set one packet period in advance of the corresponding group of incoming packets that is to be applied as input to said each switching circuit.

34. The method in claim 31 wherein said defining step comprises the step of establishing the new configuration of said each switching circuit for a corresponding group of said incoming packets that are currently being applied as input to said each switching circuit.

35. In a packet switch having "k" substantially identical input modules each providing "n" separate input ports and having "m" separate outputs, "k" substantially identical output modules each having "m" separate inputs and providing "n" separate output ports, and "m" substantially identical k-by-k cross-point switching circuits each being connected to a corresponding output of each of said input modules and to a corresponding input to each of said output modules, wherein all the corresponding outputs have the same numerical ranking and all of the corresponding inputs having the same numerical ranking, and wherein each of said incoming packets has first and second distinct address portions and a data portion therein, a method for routing packets through said switch comprising the steps of:

in each input module, applying incoming packets from said "n" input ports thereto to said "m" outputs thereof in a first pre-defined fashion;

in each output module, applying, in a second pre-defined fashion, data portions of outgoing packets from said "m" inputs thereto to said "m" output ports therefrom;

in each cross-point switching circuit;

establishing, in response to the first address portion of each of the incoming packets applied over said corresponding output from any of said "k" input modules, a route for said each incoming packet through said switching circuit and over said corresponding output to an addressed one of said "k" output modules; and

routing a portion of said each incoming packet over said route as a corresponding one of said outgoing packets to said addressed output module; and

wherein said method further comprises the step, within each of said "k" output modules, of applying, in response to the second address portion contained within said one outgoing packet applied to said each output module by any of said "m" cross-point switching circuits, the data portion contained within said one outgoing packet to an addressed one of the "n" output ports associated therewith.

36. The method in claim 35 further comprising the steps of:

prepending, in response to incoming ATM cells appearing on a user line, a predefined routing header to each of said ATM cells so as to form an associated one of said incoming packets, wherein said routing header is formed of the first and second address portions and said each ATM cell is the data portion; and

applying said associated ones of the incoming packets produced thereby to a corresponding one of said input ports.

37. The method in claim 36 wherein said prepending step further comprises the step of translating a value of a virtual channel identifier field appearing in said incoming ATM cell to produce said first and second address portions therefor.

38. The method in claim 37 wherein a packet period is formed of "m" successive intervals and said method further comprises the step of operating all the cross-point switching circuits on a time staggered basis with respect to each other such that each of said switching circuits commences routing a group of up to "k" of said incoming packets therethrough beginning at a time approximately one of said "m" intervals prior to a corresponding time at which a next successive one of said switching circuits commences routing a next successive group of up to "k" of said incoming packets therethrough.

39. The method in claim 38 wherein, in each of said input modules, said method further comprises the steps of:

storing incoming packets in a queue on a first-in first-out basis;

successively reading every one of said input ports in a round-robin fashion during a packet period and writing a current one of said incoming packets appearing on each of said input ports into successive locations in said queue; and

reading an incoming packet situated at a head of the queue in said storing step and applying, during each one of said "m" successive intervals, said incoming packet so read to a next successive one of said "m" outputs in round-robin fashion from said each input module, such that during the interval one of the switching circuits that is connected to said next successive output emanating from each of said input modules receives a group of up to "k" essentially simultaneously occurring ones of said incoming packets from all of said input modules.

40. The method in claim 39 wherein said method further comprises the step of resolving output contention among all the incoming packets then situated at the head of the queues within all the "k" input modules;

and in each of said "k" input modules said reading and applying step comprises the steps of;

sending the first address portion of an incoming packet situated at the head of the queue within said each input module to said contention resolving step; and

providing, in response to a control signal generated by said contention resolving step, the incoming packet situated at the head of the queue within said each input module to said next successive output only in the event no contention has occurred or output contention has been resolved in favor of said each input module.

41. The method in claim 40 wherein said contention resolving step further comprises the step of resolving contention during each of said "m" intervals for a corresponding one of said groups of up to "k" incoming packets, wherein each of the said groups is formed of packets then currently situated at a head of each queue within every one of said "k" input modules.

42. The method in claim 38 wherein, in each of said output modules, said method further comprises the steps of:

reading an outgoing packet appearing on each of said outputs in a round-robin fashion during a packet period;

examining, in response to said outgoing packet reading step, the second address portion in each of the outgoing packets appearing on each of said inputs, and depositing, in response to said second address portion so read, the data portion of said each outgoing packet in an end of a correspondingly addressed one of "n" first-in first-out queues; and

successively reading during a packet period the outgoing packets situated at the head of each of the "n" queues in a round-robin fashion and applying during, said packet period, each of the outgoing packets so read to a corresponding one of said output ports.

43. The method in claim 38 wherein each of said cross-point switching circuits has "k" inputs and "k" outputs and wherein, in each of said switching circuits, said method further comprises the steps of:

defining, in response to the first address portions contained within the group of up to "k" incoming packets applied to said switching circuit over said corresponding output from all of said input modules, a next successive state of all switching elements contained within said each switching circuit needed to properly route the group of "k" incoming packets through said each circuit so as to establish a new configuration thereof; and

setting, in response to a strobe signal, the state of all of said switching elements as defined by the new configuration.

44. The method in claim 43 wherein said defining step comprises the step of establishing the new configuration of said each switching circuit for a corresponding group of incoming packets in advance of the application of the corresponding group as input to said each switching circuit.

45. The method in claim 44 wherein the new configuration is set one packet period in advance of the corresponding group of incoming packets that is to be applied as input to said each switching circuit.

46. The method in claim 43 wherein said defining step comprises the step of establishing the new configuration of said each switching circuit for a corresponding group of said incoming packets that are currently being applied as input to said each switching circuit.