Apparatus and method for recovery of multiphase modulated data
First Claim
1. A clock circuit for use in recovering data from stable center portions of multiphase modulated signal components comprising:
- means for generating a signal pulse upon the transition of a first phase component of a multiphase modulated signal transmitted at a fixed bit rate;
oscillator means responsive to an error signal for generating a data clock signal having a frequency in synchronism with said bit rate;
means for delaying said data clock signal by a fixed delay of approximately one half the duration of said signal pulse to provide a delayed clock;
gate means having an enable input coupled to receive said signal pulse and a data input coupled to receive said delayed clock, for gating said delayed clock with said signal pulse to provide said error signal;
means for coupling said error signal to said oscillator means to control the data clock frequency; and
means responsive to said data clock for sampling components of said multiphase modulated signal to recover data therefrom.
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Accused Products
Abstract
A method and apparatus are provided for recovering multiphase modulated data. A signal pulse of a fixed duration is generated upon the transition of a first phase component of a multiphase modulated signal transmitted at a fixed bit rate. A data clock signal having a frequency in synchronism with the bit rate is generated in response to an error signal. The data clock signal is delayed by a delay of approximately one half the duration of the signal pulse. The delayed clock is gated using the signal pulse to provide the error signal that establishes the data clock frequency. Components of the multiphase signal are sampled using the phase locked data clock to recover data.
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Citations
20 Claims
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1. A clock circuit for use in recovering data from stable center portions of multiphase modulated signal components comprising:
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means for generating a signal pulse upon the transition of a first phase component of a multiphase modulated signal transmitted at a fixed bit rate; oscillator means responsive to an error signal for generating a data clock signal having a frequency in synchronism with said bit rate; means for delaying said data clock signal by a fixed delay of approximately one half the duration of said signal pulse to provide a delayed clock; gate means having an enable input coupled to receive said signal pulse and a data input coupled to receive said delayed clock, for gating said delayed clock with said signal pulse to provide said error signal; means for coupling said error signal to said oscillator means to control the data clock frequency; and means responsive to said data clock for sampling components of said multiphase modulated signal to recover data therefrom. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for recovering multiphase modulated data comprising the steps of:
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generating a signal pulse of a fixed duration upon the transition of a first phase component of a multiphase modulated signal transmitted at a fixed bit rate; generating a data clock signal frequency in synchronism with said bit rate in response to an error signal; delaying said data clock signal by a delay of approximately one half the duration of said signal pulse; gating said delayed clock using said signal pulse to provide said error signal; and sampling components of said multiphase signal using said data clock signal to recover data therefrom. - View Dependent Claims (9, 10, 11, 12)
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13. A QPSK data demodulator comprising:
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means for receiving a QPSK modulated data signal; means for inputting an I component of said QPSK signal to a first input of a first exclusive OR gate; means for delaying said I component by a first time period and inputting the delayed I component to a second input of said first exclusive OR gate; means for inputting a Q component of said QPSK signal to a first input of a second exclusive OR gate; means for delaying said Q component by said first time period and inputting the delayed Q component to a second input of said second exclusive OR gate; means for delaying a clock signal by a time period of approximately one half of said first time period to provide a delayed clock signal; first gate means responsive to an output from said first exclusive OR gate for gating said delayed clock signal; second gate means responsive to an output from said second exclusive OR gate for gating said delayed clock signal; means coupled to said first and second gate means for processing the gated delayed clock signal to provide an error signal; oscillator means responsive to said error signal for generating said clock signal; and means responsive to said clock signal for sampling said I and Q components to recover data carried thereby. - View Dependent Claims (14, 15)
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16. A demodulator for use in recovering data from a plurality of phase components of a multiphase modulated signal comprising:
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means for delaying a data clock signal produced by a voltage controlled oscillator to provide a delayed data clock signal; means for detecting signal transitions in a plurality of phase components of said multiphase modulated signal and generating corresponding transition detect pulses; means responsive to said transition detect pulses for gating said delayed data clock signal to produce a plurality of waveforms corresponding to said phase components, each waveform having an average value dependent on a time relationship between the delayed data clock signal and the duration of said transition detect pulses; means for summing said waveforms to produce an error signal; means responsive to said error signal for controlling the frequency of said voltage controlled oscillator; and means responsive to the data clock signal produced by said voltage controlled oscillator for sampling said phase components to recover data therefrom. - View Dependent Claims (17, 18, 19, 20)
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Specification