Apparatus and method for recovery of multiphase modulated data

• US 5,131,014 A
• Filed: 04/19/1991
• Issued: 07/14/1992
• Est. Priority Date: 04/19/1991
• Status: Expired due to Term

• Current Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Original Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Inventors: White, Charles M.
• Primary Examiner(s): Chin, Stephen
• Application Number:
  US07/688,966
• Time in Patent Office: 452 Days
• Field of Search: 375/80, 375/83, 375/84, 375/85, 375/86, 375/119, 375/120, 375/81, 375/106, 329/304, 329/307, 329/310, 331/17, 331/25, 370/105.5, 370/108
• US Class Current: 375/373
• CPC Class Codes: H04L 27/2331 wherein the received signal is demodulated using one or more delayed versions of itself

Abstract

A method and apparatus are provided for recovering multiphase modulated data. A signal pulse of a fixed duration is generated upon the transition of a first phase component of a multiphase modulated signal transmitted at a fixed bit rate. A data clock signal having a frequency in synchronism with the bit rate is generated in response to an error signal. The data clock signal is delayed by a delay of approximately one half the duration of the signal pulse. The delayed clock is gated using the signal pulse to provide the error signal that establishes the data clock frequency. Components of the multiphase signal are sampled using the phase locked data clock to recover data.

Claims

1. A clock circuit for use in recovering data from stable center portions of multiphase modulated signal components comprising:

means for generating a signal pulse upon the transition of a first phase component of a multiphase modulated signal transmitted at a fixed bit rate;

oscillator means responsive to an error signal for generating a data clock signal having a frequency in synchronism with said bit rate;

means for delaying said data clock signal by a fixed delay of approximately one half the duration of said signal pulse to provide a delayed clock;

gate means having an enable input coupled to receive said signal pulse and a data input coupled to receive said delayed clock, for gating said delayed clock with said signal pulse to provide said error signal;

means for coupling said error signal to said oscillator means to control the data clock frequency; and

means responsive to said data clock for sampling components of said multiphase modulated signal to recover data therefrom.

2. A clock circuit in accordance with claim 1 wherein said generating means comprise:

an exclusive OR gate;

means for inputting said first phase component of said multiphase modulated signal to a first input of said exclusive OR gate;

means for delaying said first phase component by a desired duration for said signal pulse; and

means for inputting the delayed first phase component to a second input of said exclusive OR gate;

wherein said exclusive OR gate outputs said signal pulse for said desired duration.

3. A clock circuit in accordance with claim 2 comprising:

a plurality of exclusive OR gates, each having a first input coupled to receive a corresponding phase component of said multiphase modulated signal and a second input coupled to receive the corresponding phase component delayed by said desired duration;

wherein said gate means are responsive to a plurality of signal pulses from said exclusive OR gates for outputting and summing a corresponding plurality of gated delayed clock signals to provide said error signal.

4. A clock circuit in accordance with claim 3 further comprising:

low pass filter means coupled to an output of said gate means for filtering the summed plurality of gated delayed clock signals; and

error amplifier means coupled to said low pass filter means for amplifying the filtered plurality of signals to provide said error signal.

5. A clock circuit in accordance with claim 1 wherein said gate means comprise a tri-state gate.

6. A clock circuit in accordance with claim 5 further comprising:

low pass filter means for filtering a signal output from said tri-state gate; and

error amplifier means for amplifying the filtered signal from said low pass filter means to provide said error signal.

7. A clock circuit in accordance with claim 1 wherein:

the duration of said signal pulse is approximately one half of a bit time established by said fixed bit rate; and

the fixed delay of said data clock is approximately one quarter of said bit time.

8. A method for recovering multiphase modulated data comprising the steps of:

generating a signal pulse of a fixed duration upon the transition of a first phase component of a multiphase modulated signal transmitted at a fixed bit rate;

generating a data clock signal frequency in synchronism with said bit rate in response to an error signal;

delaying said data clock signal by a delay of approximately one half the duration of said signal pulse;

gating said delayed clock using said signal pulse to provide said error signal; and

sampling components of said multiphase signal using said data clock signal to recover data therefrom.

9. A method in accordance with claim 8 wherein said signal pulse generating step comprises the steps of:

delaying a first phase component of said multiphase modulated signal by a time period equal to said fixed duration; and

obtaining the exclusive OR of said first phase component and the delayed first phase component to provide said signal pulse.

10. A method in accordance with claim 9 comprising the steps of:

providing a plurality of signal pulses from the exclusive ORs of a corresponding plurality of phase components and delayed phase components of said multiphase modulated signal;

generating an error derivation signal corresponding to each signal pulse by gating said delayed clock in response to each signal pulse; and

processing the error derivation signals to provide said error signal.

11. A method in accordance with claim 10 wherein said processing step comprises the steps of:

summing, low pass filtering and amplifying said error derivation signals to provide said error signal.

12. A method in accordance with claim 8 wherein said fixed duration is approximately equal to one half of a bit time established by said fixed bit rate.

13. A QPSK data demodulator comprising:

means for receiving a QPSK modulated data signal;

means for inputting an I component of said QPSK signal to a first input of a first exclusive OR gate;

means for delaying said I component by a first time period and inputting the delayed I component to a second input of said first exclusive OR gate;

means for inputting a Q component of said QPSK signal to a first input of a second exclusive OR gate;

means for delaying said Q component by said first time period and inputting the delayed Q component to a second input of said second exclusive OR gate;

means for delaying a clock signal by a time period of approximately one half of said first time period to provide a delayed clock signal;

first gate means responsive to an output from said first exclusive OR gate for gating said delayed clock signal;

second gate means responsive to an output from said second exclusive OR gate for gating said delayed clock signal;

means coupled to said first and second gate means for processing the gated delayed clock signal to provide an error signal;

oscillator means responsive to said error signal for generating said clock signal; and

means responsive to said clock signal for sampling said I and Q components to recover data carried thereby.

14. A demodulator in accordance with claim 13 wherein said first time period is equal to an amount by which said I and Q components are offset from each other.

15. A demodulator in accordance with claim 13 wherein said first and second gate means comprise tri-state gates.

16. A demodulator for use in recovering data from a plurality of phase components of a multiphase modulated signal comprising:

means for delaying a data clock signal produced by a voltage controlled oscillator to provide a delayed data clock signal;

means for detecting signal transitions in a plurality of phase components of said multiphase modulated signal and generating corresponding transition detect pulses;

means responsive to said transition detect pulses for gating said delayed data clock signal to produce a plurality of waveforms corresponding to said phase components, each waveform having an average value dependent on a time relationship between the delayed data clock signal and the duration of said transition detect pulses;

means for summing said waveforms to produce an error signal;

means responsive to said error signal for controlling the frequency of said voltage controlled oscillator; and

means responsive to the data clock signal produced by said voltage controlled oscillator for sampling said phase components to recover data therefrom.

17. A demodulator in accordance with claim 16 wherein said data clock signal is delayed by approximately one half the duration of said transition detect pulses.

18. A demodulator in accordance with claim 17 wherein said sampling means sample said phase components in the center of successive data pulses carried thereby.

19. A demodulator in accordance with claim 16 wherein said gating means comprise a tri-state gate for each phase component, each tri-state gate having an enable input coupled to receive the transition detect pulses for the corresponding phase component and a data input coupled to receive said delayed data clock signal.

20. A demodulator in accordance with claim 19 wherein said data clock signal is delayed by approximately one half the duration of said transition detect pulses.