Combined BAUD rate generator and digital phase locked loop
First Claim
1. A combined BAUD rate generator and phase locked loop circuit capable of operating in either a synchronous or an asynchronous mode, the combined circuit comprising:
- a single BAUD rate generator for generating a sampling signal having a selected BAUD rate, wherein said BAUD rate generator receives a clocking signal used to generator said sampling signal and wherein said clocking signal is generated by an external clock generating means;
phase adjusting means connected to said BAUD rate generator for increasing or decreasing the BAUD rate of said BAUD rate generator as a function of the phase difference between said sampling signal and a received data stream; and
mode selecting means coupled to said BAUD rate generator and to said phase adjusting means for selecting either asynchronous operation or synchronous operation of said combined circuit depending upon an externally generated mode selecting signal;
wherein said phase adjusting means controls the phase of said sampling signal during the synchronous mode and wherein said phase adjusting means does not control the phase of said sampling signal during the asynchronous mode.
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Accused Products
Abstract
A combined BAUD rate generator and digital phase locked loop (DPLL) circuit operates in either an asynchronous BAUD rate generating mode or a synchronous phase-locked mode. The combination circuit requires less circuitry than a functionally equivalent circuit with a separate BAUD rate generator and DPLL. The combination circuit comprises a count register, a period register, a decrementing/incrementing circuit, a phase adjusting circuit, and a clock option register. In a first operating mode, the combination circuit functions as a programmable BAUD rate generator which may be used for asynchronous communication applications. In a second operating mode, the combination circuit functions as both a programmable BAUD rate generator and a digital phase locked loop that may be used for synchronous communication applications and that includes an improved method for phase locking a sampling signal to an input signal. The combination circuit utilizes the same period register, count register, clock option register, and other common circuitry, during both the BAUD rate generating mode and the phase locked mode.
41 Citations
8 Claims
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1. A combined BAUD rate generator and phase locked loop circuit capable of operating in either a synchronous or an asynchronous mode, the combined circuit comprising:
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a single BAUD rate generator for generating a sampling signal having a selected BAUD rate, wherein said BAUD rate generator receives a clocking signal used to generator said sampling signal and wherein said clocking signal is generated by an external clock generating means; phase adjusting means connected to said BAUD rate generator for increasing or decreasing the BAUD rate of said BAUD rate generator as a function of the phase difference between said sampling signal and a received data stream; and mode selecting means coupled to said BAUD rate generator and to said phase adjusting means for selecting either asynchronous operation or synchronous operation of said combined circuit depending upon an externally generated mode selecting signal; wherein said phase adjusting means controls the phase of said sampling signal during the synchronous mode and wherein said phase adjusting means does not control the phase of said sampling signal during the asynchronous mode. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A digital phase locked loop circuit for adjusting the phase of a sampling clock signal depending upon the phase of a received data stream comprising:
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means for generating said sampling clock signal; a counting means having an incrementing mode and a decrementing mode, said counting means both incrementing and decrementing a count value in a predetermined sequence during each cycle of the sampling clock signal; and a phase adjusting circuit connected to said counting means for changing the count value depending upon the count value at a time when a transition of the received data stream occurs.
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Specification