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Counter circuit with two tri-state latches

  • US 5,131,018 A
  • Filed: 07/31/1990
  • Issued: 07/14/1992
  • Est. Priority Date: 07/31/1990
  • Status: Expired due to Term
First Claim
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1. A counter circuit to count data bits, comprising:

  • a first tri-state inverter for receiving the data bits and their complements;

    a first tri-state latch for receiving the data bits and their complements, connected to the output of the first tri-state inverter;

    a second tri-state inverter for receiving the data bits and their complements, connected to the output of the first tri-state inverter; and

    a second tri-state latch for receiving the data bits and their complements, connected to the output of the second tri-state inverter, its output forming the output of the circuit, its output fedback to the first tri-state inverter.

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