Counter circuit with two tri-state latches
First Claim
1. A counter circuit to count data bits, comprising:
- a first tri-state inverter for receiving the data bits and their complements;
a first tri-state latch for receiving the data bits and their complements, connected to the output of the first tri-state inverter;
a second tri-state inverter for receiving the data bits and their complements, connected to the output of the first tri-state inverter; and
a second tri-state latch for receiving the data bits and their complements, connected to the output of the second tri-state inverter, its output forming the output of the circuit, its output fedback to the first tri-state inverter.
1 Assignment
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Accused Products
Abstract
A counter circuit is disclosed. The circuit has a first tri-state inverter for receiving data bits and their components. It includes a first tri-state latch for receiving the data bits and their complements, connected to the output of the first tri-state inverter. It has a second tri-state inverter for receiving the data bits and their complements that is connected to the output of the first tri-state latch. It includes a second tri-state latch for receiving the data bits and their complements. The second tri-state latch is connected to the output of the second tri-state inverter. Its output is the output of the circuit, and, its output is fedback to the first tri-state inverter. Such a circuit is useful in setting an internal address of a dynamic memory device during a CBR cycle.
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Citations
8 Claims
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1. A counter circuit to count data bits, comprising:
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a first tri-state inverter for receiving the data bits and their complements; a first tri-state latch for receiving the data bits and their complements, connected to the output of the first tri-state inverter; a second tri-state inverter for receiving the data bits and their complements, connected to the output of the first tri-state inverter; and a second tri-state latch for receiving the data bits and their complements, connected to the output of the second tri-state inverter, its output forming the output of the circuit, its output fedback to the first tri-state inverter. - View Dependent Claims (2)
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3. A divide by two circuit, comprising:
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a first tri-state inverter for receiving data bits and the complements, having an enable terminal; a first tri-state latch for receiving data bits and their complements, having an enable terminal; a second tri-state inverter for receiving data bits and the complements, having an enable terminal; a second tri-state latch for receiving data bits and their complements, having an enable terminal; the output of the first tri-state inverter connected to the first tri-state latch and connected to the enable terminal of the second tri-state inverter; the output of the first tri-state latch connected to the enable terminal of the first tri-state latch; and the output of the second tri-state latch connected to the enable terminal of the first tri-state inverter and connected to the enable terminal of the second tri-state latch. - View Dependent Claims (4, 5, 6, 7)
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8. An integrated circuit dynamic memory device, comprising:
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an array of memory cells; periphery circuitry to read information from the memory cells and write information to the memory cells; the periphery circuitry including circuitry to generate RAS, CAS, and CBR timing signals, and including a circuit whose input is coupled to the CBR timing signal and is responsive to perform an incremental binary count to set a CBR internal address during a CBR cycle, the circuit comprising; a first tri-state inverter for receiving the CBR timing signals and the complements of the CBR timing signals; a first tri-state latch for receiving the CBR timing signals and the complements, connected to the output of the first tri-state inverter; a second tri-state inverter for receiving the CBR timing signals and their complements, connected to the output of the first tri-state latch; and a second tri-state latch for receiving the CBR timing signals and their complements, connected to the output of the tri-state inverter, its output forming the output of the circuit, its output fedback to the first tri-state inverter; the output of the first tri-state latch being fedback to the first tri-state latch; and the output of the second tri-state latch is fedback to the second tri-state latch.
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Specification