Counter circuit with two tri-state latches

• US 5,131,018 A
• Filed: 07/31/1990
• Issued: 07/14/1992
• Est. Priority Date: 07/31/1990
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: McAdams, Hugh P., Tabacco, Paolo
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US07/560,983
• Time in Patent Office: 714 Days
• Field of Search: 377/121, 377/118, 377/117, 377/116, 377/115, 365/236
• US Class Current: 377/117
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence

Abstract

A counter circuit is disclosed. The circuit has a first tri-state inverter for receiving data bits and their components. It includes a first tri-state latch for receiving the data bits and their complements, connected to the output of the first tri-state inverter. It has a second tri-state inverter for receiving the data bits and their complements that is connected to the output of the first tri-state latch. It includes a second tri-state latch for receiving the data bits and their complements. The second tri-state latch is connected to the output of the second tri-state inverter. Its output is the output of the circuit, and, its output is fedback to the first tri-state inverter. Such a circuit is useful in setting an internal address of a dynamic memory device during a CBR cycle.

Claims

1. A counter circuit to count data bits, comprising:

a first tri-state inverter for receiving the data bits and their complements;

a first tri-state latch for receiving the data bits and their complements, connected to the output of the first tri-state inverter;

a second tri-state inverter for receiving the data bits and their complements, connected to the output of the first tri-state inverter; and

a second tri-state latch for receiving the data bits and their complements, connected to the output of the second tri-state inverter, its output forming the output of the circuit, its output fedback to the first tri-state inverter.

2. The counter circuit of claim 1 wherein:

the output of the first tri-state latch is fedback to the first tri-state latch;

the output of the second tri-state latch is fedback to the second tri-state latch.

3. A divide by two circuit, comprising:

a first tri-state inverter for receiving data bits and the complements, having an enable terminal;

a first tri-state latch for receiving data bits and their complements, having an enable terminal;

a second tri-state inverter for receiving data bits and the complements, having an enable terminal;

a second tri-state latch for receiving data bits and their complements, having an enable terminal;

the output of the first tri-state inverter connected to the first tri-state latch and connected to the enable terminal of the second tri-state inverter;

the output of the first tri-state latch connected to the enable terminal of the first tri-state latch; and

the output of the second tri-state latch connected to the enable terminal of the first tri-state inverter and connected to the enable terminal of the second tri-state latch.

4. The divide by two circuit of claim 3 wherein the first tri-state inverter comprises:

a first P-channel transistor and a second P-channel transistor connected in series, the first P-channel transistor having one terminal connected to a voltage source;

a first N-channel transistor and a second N-channel transistor connected in series, the second N-channel transistor having one terminal connected to ground;

the second P-channel transistor being connected to the first N-channel transistor;

the gate of the first P-channel transistor and the gate of the second N-channel transistor being connected together to form the enable terminal; and

the gate of the second P-channel transistor connected to the complemented data bits, the gate of the first N-channel transistor connected to the data bits.

5. The divide by two circuit of claim 4 wherein the first tri-state latch comprises:

a first P-channel transistor and a second P-channel transistor connected in series, the first P-channel transistor having one terminal connected to a voltage source;

a first N-channel transistor and a second N-channel transistor connected in series, the second N-channel transistor having one terminal connected to ground;

the second P-channel transistor connected to the first N-channel transistor;

the gate of the second P-channel transistor being connected to the data bits, the gate of the first N-channel transistor being connected to the complemented data bits; and

an inverter, whose input is connected to second P-channel transistor and to the first N-channel transistor, and whose output is connected to the gates of the first P-channel transistor and the second N-channel transistor.

6. The divide by two circuit of claim 5 wherein the second inverter comprises:

a first P-channel transistor and a second P-channel transistor connected in series, the first P-channel transistor having one terminal connected to a voltage source;

a first N-channel transistor and a second N-channel transistor connected in series, the second N-channel transistor having one terminal connected to ground;

the second P-channel transistor connected to the first N-channel transistor;

the gate of the second P-channel transistor connected to the data bits, the gate of the first N-channel transistor connected to the complemented data bits; and

the gates of the first P-channel transistor and the second N-channel transistor being connected together and connected to the input of the inverter of the first tri-state latch.

7. The divide by two circuit of claim 6 wherein the second tri-state latch comprises:

a first P-channel transistor and a second P-channel transistor connected in series, the first P-channel transistor having one terminal connected to a voltage source;

a first N-channel transistor and a second N-channel transistor connected in series, the second N-channel transistor having one terminal connected to ground;

the second P-channel transistor connected to the first N-channel transistor;

the gate of the second P-channel transistor connected to the complemented data bits, the gate of the first N-channel transistor connected to the data bits;

an inverter whose input is connected to the second P-channel transistor and to the first N-channel transistor, and whose output is connected to the gates of the first P-channel transistor and the second N-channel transistor, and connected to the gates of the first P-channel transistor and the second N-channel transistor of the first tri-state inverter.

8. An integrated circuit dynamic memory device, comprising:

an array of memory cells;

periphery circuitry to read information from the memory cells and write information to the memory cells;

the periphery circuitry including circuitry to generate RAS, CAS, and CBR timing signals, and including a circuit whose input is coupled to the CBR timing signal and is responsive to perform an incremental binary count to set a CBR internal address during a CBR cycle, the circuit comprising;

a first tri-state inverter for receiving the CBR timing signals and the complements of the CBR timing signals;

a first tri-state latch for receiving the CBR timing signals and the complements, connected to the output of the first tri-state inverter;

a second tri-state inverter for receiving the CBR timing signals and their complements, connected to the output of the first tri-state latch; and

a second tri-state latch for receiving the CBR timing signals and their complements, connected to the output of the tri-state inverter, its output forming the output of the circuit, its output fedback to the first tri-state inverter;

the output of the first tri-state latch being fedback to the first tri-state latch; and

the output of the second tri-state latch is fedback to the second tri-state latch.