Fault tolerant interconnection networks

• US 5,131,041 A
• Filed: 11/30/1989
• Issued: 07/14/1992
• Est. Priority Date: 11/30/1989
• Status: Expired due to Fees

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.), Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: AT&T, Inc.
• Inventors: Brunner, Beat, Kumar, Vijay P.
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Jung, Min
• Application Number:
  US07/444,581
• Time in Patent Office: 957 Days
• Field of Search: 370/60, 370/65.5, 370/63, 370/58.1, 370/58.2
• US Class Current: 370/219
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/557 Error correction, e.g. fault recovery or fault tolerance

Abstract

A multi-stage, alternate routing switching network is enhanced with a switch architecture that is able to detect and mask all single faults. The switch employs a controller that develops dual rail control signals. In one embodiment, the controller is made up of two controllers that receive the same inputs but generate complementary outputs. The complementary outputs form the dual rail signals that control the multiplexers that are interposed between the inputs and the outputs of the switch. The dual rail control of the signal routing within the switch allow for effective detection of all signal faults in the signal routing means. Inclusion of totally self checking circuits at the switch outputs as well as inputs enables users to readily isolate a fault and identify its source.

Claims

1. A multi-stage switching network with switches in each stage connected to switches in another stage, where at least one of said switches comprises:

a switching module for routing signals applied to an input port of said switch to an output port of said switch,

an output protocol port associated with said output port of said switch and an input protocol port associated with said input port of said switch, and

a control module for generating dual rail internal control signals and for controlling said switching module through dual rail signal lines carrying said internal control signals.

2. The switching network of claim 1 wherein said control module further controls interactions of said switch with other switches connected to the switch through external control lines comprising dual rail signal lines, which external control lines are coupled to said input protocol port and said output protocol port.

3. The switching network of claim 1 wherein said control module further controls interactions of said switch with other switches connected to the switch through external control lines comprising dual rail signal lines and m-out-of-n signal line groups, which external control lines are coupled to said input protocol port and said output protocol port.

4. The switching network of claim 3 wherein said control module further comprises:

means for receiving indication from said output protocol port that a switch connected to said output port is occupied and for communicating that indication through said input protocol port to a switch connected to said input port, and

means for receiving information from said input protocol port and said input port that a switch connected to said input port is in the midst of sending a packet of data but has no data available for transmission and for communicating that information through said output protocol port and said output port.

5. The switching network of claim 1 wherein said switching module includes a parity checker at said input port of said switch and at said output port of said switch, and means for communicating error indications developed by said parity checkers to said control module.

6. The switching network of claim 5 wherein said parity checkers develop said error indications in dual rail form.

7. The switching network of claim 5 wherein said control module includes means for combining the error indications of said parity checkers and for modifying said interactions of said switch with other switches in response thereto.

8. The switching network of claim 5 wherein said parity checkers are totally-self-checking parity checkers.

9. The switching network of claim 5 wherein said control module generates a fault signal corresponding to said error indications and sends the fault signal to one of said protocol ports.

10. The switching network of claim 1 wherein said switching module comprises:

a buffer module connected to said input port and a signal routing module interposed between said buffer module and said output port.

11. The switching network of claim 1 wherein said switching module comprises

at least two branches, each of which having an input line and an output line, with the input line responsive to an input signal and the output line connected to a selection means, and

two complementary switches, connected in parallel and interposed between said input line and said output line, under control of a dual rail internal control signal pair from said control module, with one signal of said pair controlling one of said switches and the other signal of said pair controlling the other of said switches.

12. A switch having at least two signal input ports and at least two signal output ports, for routing signals applied to said signal input ports to said signal output ports comprising:

an input protocol port for interfacing said switch with sources that apply signals to said input signal ports, and an output protocol port for interfacing said switch with destinations to which output signals of said output signal ports are delivered;

a switching module for routing signals applied to said signal input ports to said signal output ports, and

a control module for generating dual rail signals and for controlling said switching module through said dual rail signal lines and for controlling interactions of said switch with said sources and said destinations through dual rail signal lines.

13. The switch of claim 12 wherein said control module further controls interactions of said switch with other switches connected to the switch in response to dual rail control signals received through said input protocol port and said output protocol port.

14. The switch of claim 12 wherein said control module further controls interactions of said switch with other switches connected to the switch in response to external control signals comprising dual rail control signals and m-out-of-n signal groups, which external control signals are received through said input protocol port and said input protocol port.

15. The switch of claim 14 wherein said control module further comprises:

means for receiving indication from said output protocol port that a switch connected to one of said signal output ports is occupied and for communicating that indication through said input protocol port to a switch connected to one of said signal input ports, and

means for receiving information from said input protocol port and said signal input port that a switch connected to said signal input port is in the midst of sending a packet of data but has no data available for transmission and for communicating that information through said output protocol port and said signal output port.

16. The switch of claim 12 wherein said routing module includes a parity checker at each signal input port of said switch and at each signal output port of said switch, and means for communicating error indications developed by said parity checkers to said control module.

17. The switch of claim 16 wherein said parity checkers develop said error indications in dual rail form.

18. The switch of claim 16 wherein said control module includes means for combining the error indications of said parity checkers and for modifying said interactions of said switch with other switches in response thereto.

19. The switch of claim 16 wherein said parity checkers are totally-self-checking parity checkers.

20. The switch of claim 12 wherein said switching module comprises:

a buffer module connected to said signal input ports and a signal routing module interposed between said buffer module and said signal output ports, wherein said buffer module comprises;

a first buffer stage for storing information received by said switch at said signal input ports,

a second buffer stage for storing information received from said first buffer stage, and

means for selecting the information stored in one of said buffer stages for delivery by said switching module.

21. The switch of claim 12 wherein said switching module comprises

at least two branches, each of which having an input line and an output line, with the input line responsive to an input signal and the output line connected to a selecting means, and

two complementary switches, connected in parallel and interposed between said input line and said output line, under control of a dual rail signal pair from said control module, with one signal of said pair controlling one of said switches and the other signal of said pair controlling the other of said switches.