Neuron unit and neuron unit network

• US 5,131,073 A
• Filed: 07/10/1990
• Issued: 07/14/1992
• Est. Priority Date: 07/12/1989
• Status: Expired due to Term

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Horiguchi, Hiroyuki, Eguchi, Hirotoshi, Furuta, Toshiyuki
• Primary Examiner(s): MacDonald, Allen R.
• Application Number:
  US07/550,404
• Time in Patent Office: 735 Days
• Field of Search: 364/513, 364/807, 307/201, 382/14, 382/15, 395/27
• US Class Current: 706/42
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A neuron unit simultaneously processes a plurality of binary input signals. The neuron unit includes input lines for receiving first and second input signals which undergo transitions with time, first and second memories for storing weighting coefficients, a first gate for successively obtaining a logical product of one of the first input signals and a corresponding one of the weighting coefficients read out from the first memory for each of the first input signals, a second gate for successively obtaining a logical product of one of the second input signals and a corresponding one of the weighting coefficients read out from the second memory for each of the second input signals, a third gate for obtaining a logical sum of logical products output from the first gate, a fourth gate for obtaining a logical sum of logical products output from the second gate, and an output part including an inverter for inverting the logical sum output from the fourth gate and a gate for obtaining one of a logical product and a logical sum of the logical sum output from the third gate and an inverted logical sum output from the inverter. This gate outputs an output signal of the neuron unit.

Claims

1. A neuron unit network comprising:

(A) a plurality of neuron units which are coupled to form a hierarchical structure which has a plurality of layers; and

(B) a plurality of signal liens coupling outputs of arbitrary neuron units in one layer of the hierarchical structure to inputs of arbitrary neuron units in another layer of the hierarchical structure, each of said neuron units simultaneously processing a plurality of binary input signals and outputting an output signal which is indicative of a result of the processing, said neuron unit including;

a) a plurality of input lines connected to provide binary input signals which undergo transitions with time;

b) memory means for storing;

1) weighting coefficients; and

2) corresponding grouping information, said grouping information indicating one of the excitation and inhibition groups to which said weighting coefficients belong;

c) first digital gate means, responsive to said memory means and said input lines, for outputting logical product of;

1) one of said binary input signals received from said input lines; and

2) a corresponding one of the weighting coefficients from said first memory means;

for each of said binary input signals;

d) second digital gate means, responsive to said memory means, for outputting a logical product of;

1) one of said grouping information from said memory means; and

2) a corresponding one of logical products output from said first digital gate means;

for each of the logical products output from said first digital gate means;

e) third digital gate means, responsive to said memory means, for outputting a logical product of;

1) an inversion of one of said grouping information from said memory means; and

2) a corresponding one of the logical products output from said first digital gate means;

for each of the logical products output from said first digital gate means;

f) fourth digital gate means, responsive to said second digital gate means, for outputting a logical sum of logical products output from said second digital gate means;

g) fifth digital gate means, responsive to said third digital gate means, for outputting a logical sum of logical products output from said third digital gate means; and

h) output means including;

1) a digital inverter, responsive to said fifth digital gate means, for inverting the logical sum output from said fifth digital gate means; and

2) a digital gate, responsive to said fourth digital gate means and said digital inverter, for outputting one of

A) a logical product of; and

B) a logical sum of

i) the logical sum output from said fourth digital gate means; and

ii) an inverted logical sum output from said digital inverter,

said digital gate outputting the output signal of said neuron unit.

2. An apparatus including the neuron unit network as claimed in claim 1, comprising:

means for providing said binary input signals which respectively describe a signal quantity in a form of a pulse density; and

said memory means includes means for storing the weighting coefficients which respectively describe a signal quantity in a form of a pulse density.

3. The apparatus as claimed in claim 2 wherein the memory means includes means for storing each weighting coefficient having a pulse density defined by a number of first values and second values within a predetermined time, the first values and second values being arranged at random, and the first and second values respectively corresponding to high and low binary signal levels.

4. A neuron unit for simultaneously processing a plurality of input signals on a plurality of respective input lines, and for outputting on a neuron unit output a neuron unit output signal which is indicative of a result of the processing, the neuron unit comprising:

a) the plurality of input lines;

b) a plurality of first memory devices having respective first memory outputs;

c) a plurality of second memory devices having respective second memory outputs;

d) a plurality of first digital NOT circuits, connected to respective second memory outputs, and having respective first digital NOT outputs;

e) a plurality of first digital AND circuits, connected to respective input lines and to respective first memory outputs, and having respective first digital AND outputs;

f) a plurality of second digital AND circuits, connected to respective first digital AND outputs and to respective second memory outputs, and having respective second digital AND outputs;

g) a plurality of third digital AND circuits, connected to respective first digital AND outputs and to respective first digital NOT outputs, and having respective third digital AND outputs;

h) a first digital OR circuit, connected to the second digital AND outputs, and having a first digital OR output;

i) a second digital OR circuit, connected to the third digital AND outputs, and having a second digital OR output;

j) a second digital NOT circuit, connected to the second digital OR output, and having a second digital NOT output; and

k) a fourth digital AND circuit, connected to the first digital OR output and to the second digital NOT output, and having an output constituting the neuron unit output.

5. A neuron unit for simultaneously processing a plurality of binary input signals on a plurality of input lines, and for outputting on a neuron unit output a neuron unit output signal which is indicative of a result of the processing, the neuron unit comprising:

a) the plurality of input lines;

b) a plurality of first memory devices having respective first memory outputs;

c) a plurality of second memory devices having respective second memory outputs;

d) a plurality of first digital NOT circuits, connected to respective second memory outputs, and having respective first digital NOT outputs;

e) a plurality of first digital AND circuits, connected to respective input lines and to respective first memory outputs; and

having respective first digital AND outputs;

f) a plurality of second digital AND circuits, connected to respective first digital AND outputs and to respective second memory outputs, and having respective second digital AND outputs;

g) a plurality of third digital AND circuits, connect to respective first digital AND outputs and to respective first digital NOT outputs, and having respective third digital AND outputs;

h) a first digital OR circuit, connected to the second digital AND outputs, and having a first digital OR output;

i) a second digital OR circuit, connected to the third digital AND outputs, and having a second digital OR output;

j) a second digital NOT circuit, connected to the second digital OR output, and having a second digital NOT output; and

k) a third digital OR circuit, connected to the first digital OR output and to the second digital NOT output, and having an output constituting the neuron unit output.

6. A neuron unit network, comprising:

A) A plurality of neuron units which are coupled to form a hierarchical structure that has a plurality of layers; and

B) a plurality of signals lines coupling neuron unit outputs of arbitrary neuron units in one layer of the hierarchical structure to a plurality of input lines of arbitrary neuron units in another layer of the hierarchical structure, each of said neuron units having a neuron unit output, each of said neuron units including;

a) the plurality of input lines;

b) a plurality of first memory devices having respective first memory outputs;

c) a plurality of second memory devices having respective second memory outputs;

d) a plurality of first digital NOT circuits, connected to respective second memory outputs, and having respective first digital NOT outputs;

e) a plurality of first digital AND circuits, connected to respective input lines and to respective first memory outputs, and having respective first digital AND outputs;

f) a plurality of second digital AND circuits, connected to respective first digital AND outputs and to respective second memory outputs, and having respective second digital AND outputs;

g) a plurality of third digital AND circuits, connected to respective first digital AND outputs and to respective first digital a plurality of NOT outputs, and having respective third digital AND outputs;

h) a first digital OR circuit, connected to the second digital AND outputs, and having a first digital OR output;

i) a second digital OR circuit, connected to the third digital AND outputs, and having a second digital OR output;

j) a second digital NOT circuit, connected to the second digital OR output, and having a second digital NOT output; and

k) a fourth digital AND circuit, connected to the first digital OR output and to the second digital NOT output, and having an output constituting the neuron unit output.

7. A neuron unit for simultaneously processing a plurality of binary input signals and for outputting an output signal which is indicative of a result of the processing, said neuron unit comprising:

a) a plurality of input lines connected to provide binary input signals which undergo transitions with time;

b) memory means for storing;

1) weighting coefficients; and

2) corresponding grouping information, said grouping information indicating one of excitation and inhibition groups to which said weighting coefficients belong;

c) first digital gate means, responsive to said memory means and said input lines, for outputting a logical product of;

1) one of said binary input signals received from said input lines; and

2) a corresponding one of the weighting coefficients from said first memory means;

for each of said binary input signals;

d) second digital gate means, responsive to said memory means, for outputting a logical product of;

1) one of said grouping information from said memory means; and

2) a corresponding one of logical products output from said first digital gate means;

for each of the logical products output from said first digital gate means;

e) third digital gate means, responsive to said memory means, for outputting a logical product of;

1) an inversion of one of said grouping information from said memory means; and

2) a corresponding one of the logical products output from said first digital gate means;

for each of the logical products output from said first digital gate means;

f) fourth digital gate means, responsive to said second digital gate means, for outputting a logical sum of logical products output from said second digital gate means;

g) fifth digital gate means, responsive to said third digital gate means, for outputting a logical sum of logical products output from said third digital gate means; and

h) output means including;

1) a digital inverter, responsive to said fifth digital gate means, for inverting the logical sum output from said fifth digital gate means; and

2) a digital gate, responsive to said fourth digital gate means and said digital inverter, for outputting one of

A) a logical product of; and

B) a logical sum of;

i) the logical sum output from said fourth digital gate means; and

ii) an inverted logical sum output from said digital inverter,

said digital gate outputting the output signal of said neuron unit.

8. An apparatus including the neuron unit as claimed in claim 7, comprising:

means for providing said binary input signals which respective describe a signal quantity in a form of a pulse density; and

said memory means includes means for storing the weighting coefficients which respectively describe a signal quantity in a form of a pulse density.

9. The apparatus as claimed in claim 8 wherein the memory means includes means for storing each weighting coefficient having a pulse density defined by a number of first values and second values within a predetermined time, the first values and second values being arranged at random, and the first and second values respectively corresponding to high and low binary signal levels.

10. The neuron unit as claimed in claim 7 wherein said memory means includes a storage capacity of at least three bits for one weighting coefficient and a corresponding grouping information.

11. The neuron unit as claimed in claim 10 wherein said memory means includes shift registers each having a storage capacity of at least two bits for storing the weighting coefficients, and 1-bit memories for storing the grouping information.

12. The neuron unit as claimed in claim 11 wherein said memory means respectively use a content of each shift register repeatedly.

13. A neuron unit network, comprising:

A) a plurality of neuron units that are coupled to form a hierarchical structure which has a plurality of layers; and

B) a plurality of signals lines coupling neuron unit outputs of arbitrary neuron units in one layer of the hierarchical structure to a plurality of input lines of arbitrary neuron units in another layer of the hierarchical structure, each of said neuron units having a neuron unit output, each of said neuron units including;

a) the plurality of input lines;

b) a plurality of first memory devices having respective first memory outputs;

c) a plurality of second memory devices having respective second memory outputs;

d) a plurality of first digital NOT circuits, connected to respective second memory outputs, and having respective first digital NOT outputs;

e) a plurality of first digital AND circuits, connected to respective input lines and to respective first memory outputs; and

having respective first digital AND outputs;

f) a plurality of second digital AND circuits, connected to respective first digital AND outputs and to respective second memory outputs, and having respective second digital AND outputs;

g) a plurality of third digital AND circuits, connect to respective first digital AND outputs and to respective first digital NOT outputs, and having respective third digital AND outputs;

h) a first digital OR circuit, connected to the second digital AND outputs, and having a first digital OR output;

i) a second digital OR circuit, connected to the third digital AND outputs, and having a second digital OR output;

j) a second digital NOT circuit, connected to the second digital OR output, and having a second digital NOT output; and

k) a third digital OR circuit, connected to the first digital OR output and to the second digital NOT output, and having an output constituting the neuron unit output.