Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs

• US 5,132,753 A
• Filed: 03/23/1990
• Issued: 07/21/1992
• Est. Priority Date: 03/23/1990
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Owyang, King, Chang, Mike F.
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): Potter, Roy
• Application Number:
  US07/498,170
• Time in Patent Office: 851 Days
• Field of Search: 357/23.4, 357/90, 357/23.8, 357/23.4
• US Class Current: 257/655
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

Transistor structure using a lightly doped drain (LDD) technique are disclosed. The present invention provides a reduced on-resistance in the LDD region, while retaining substantially all the high breakdown voltage advantage of the LDD technique. The advantage of the present invention is achieved by applying a non-uniform impurity design in the LDD region, increasing gradually from the gate-edge towards the contact.

Claims

1. A field effect transistor, comprising:

a substrate of a first conductivity type having a surface;

a first source/drain region embedded in the surface of the substrate and of a second conductivity type, opposite to the first conductivity type;

a second source/drain region embedded in the surface of the substrate, and separated from the first source/drain region, the second source/drain region being of the second conductivity type;

a gate region above the surface of the substrate, separated from the surface by an insulator region;

a channel region underneath said gate region, said channel region being of one of first and second channel types; and

a lightly doped drift region between the channel region and the second source/drain region, the lightly doped region being of the second conductivity type, and having a graded impurity concentration generally increasing from an edge of the lightly doped drift region adjacent the channel towards an edge of the lightly doped drift region adjacent the second source/drain region, thereby substantially reducing on-resistance in said lightly doped drift region.

2. A field effect transistor as recited in claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

3. A field effect transistor as recited in claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

4. A field effect transistor as recited in claim 1, wherein the lightly doped drift region further comprises a plurality of subregions each having a different impurity concentration, the subregions located such that the most lightly doped subregion is closest to the edge of the lightly doped drift region adjacent the channel, and each successive subregion further distal from the channel and more proximal to the second source/drain region having successively higher impurity concentrations.

5. A field effect transistor as recited in claim 1, wherein the lightly doped drift region further comprises a plurality of subregions each having a uniform impurity concentration, the subregions located such that the average impurity concentration over subregions closer to the channel than the second source/drain region is less than the average impurity concentration of the subregions closer to the second source/drain region than the channel.

11. A field effect transistor as recited in claim 5, wherein the first lightly doped drift region further comprises a plurality of subregions each having uniform impurity concentration, the subregions located such that the average impurity concentration over subregions closer to the channel than the first source/drain region is less than the average impurity concentration of the subregions closer to the first source/drain region than the channel.

12. A field effect transistor as recited in claim 5, wherein the second lightly doped drift region further comprises a plurality of subregions each having a uniform impurity concentration, the subregions located such that the average impurity concentration over subregions closer to the channel than the second source/drain region is less than the average impurity concentration of the subregions closer to the second source/drain region than the channel.

6. A field effect transistor, comprising:

a substrate of a first conductivity type having a surface;

a first source/drain region embedded in the surface of the substrate and of a second conductivity type, opposite to the first conductivity type;

a second source/drain region embedded in the surface of the substrate, and separated from the first source/drain region, the second source/drain region being of the second conductivity type;

a gate region above the surface of the substrate, separated from the surface by an insulator region;

a channel region underneath said gate region, said channel region being of one of first and second channel types;

a first lightly doped drift region between the channel region and the second source/drain region, the first lightly doped drift region being of the second conductivity type, and having a graded impurity concentration generally increasing from an edge of the first lightly doped drift region adjacent the channel towards an edge of the first lightly doped drift region adjacent the second source/drain region, thereby substantially reducing on-resistance in said first lightly doped drift region; and

a second lightly doped drift region between the channel and the first source/drain region, the second lightly doped drift region being of the second conductivity type, and having a graded impurity concentration generally increasing from an edge of the second lightly doped drift region adjacent to the channel towards an edge of the second lightly doped drift region adjacent the first source/drain region, thereby substantially reducing on-resistance in said second lightly doped drift region.

7. A field effect transistor as recited in claim 6, wherein the first conductivity type is n-type and the second conductivity type is p-type.

8. A field effect transistor as recited in claim 6, wherein the first conductivity type is p-type and the second conductivity type is n-type.

9. A field effect transistor as recited in claim 6, wherein the first lightly doped drift region further comprises a plurality of subregions each having a different impurity concentration, the subregions located such that the most lightly doped subregion is closest to the edge of the first lightly doped drift region adjacent the channel, and each successive subregion further distal from the channel and more proximal to the second source/drain region having successively higher impurity concentrations.

10. A field effect transistor as recited in claim 6, wherein the second lightly doped drift region further comprises a plurality of subregions each having a different impurity concentration, the subregions located such that the most lightly doped subregion is closest to the edge of the second lightly doped drift region adjacent the channel, and each successive subregion further distal from the channel and more proximal to the first source/drain region having successively higher impurity concentrations.