Interleaved bridge converter

• US 5,132,888 A
• Filed: 01/07/1991
• Issued: 07/21/1992
• Est. Priority Date: 01/07/1991
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Mulkern, Joseph H., Lo, David S.
• Primary Examiner(s): Stephan, Steven L.
• Assistant Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US07/637,735
• Time in Patent Office: 561 Days
• Field of Search: 363/17, 363/98, 363/132
• US Class Current: 363/17
• CPC Class Codes: H02M 1/0064 Magnetic structures combining different functions, e.g. storage, filtering or transformation
• CPC Class Codes: H02M 3/01 Resonant DC/DC converters
• CPC Class Codes: H02M 3/33573 Full-bridge at primary side of an isolation transformer
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A DC to DC power converter is implemented which includes an input switching circuit, an input capacitor, a transformer and an output rectifying switching circuit coupled to the transformer. The input switching circuit consists of a minimum of four transistors which are operated in a timed relationship such that bi-directional currents are developed in both primary windings. The output rectifying switching circuit is operated with switching transistors that provide zero-voltage resonant transition (ZVRT) switching. Timing relationships between the input signals control the ZVRT with switching of the transistors. Bidirectional currents in the primary windings of the single transformer element permit a reduction in volume of the magnetic element and the coils of the transformer for a given level of output power. Overall, converter volume for a given output power is thereby sufficiently reduced to allow a power converter to be mounted on a circuit board, which enables a practical embodiment of a distributed power processing system.

Claims

1. In a full-bridge DC-DC power converter coupled to an input DC voltage source for converting input power and supplying DC output voltage to a load in which said converter consists of

first, second, third and fourth field-effect transistors each of which comprises a gate for controlling the switching of said transistor off and on and a source-drain path which provides a current path when said transistor is switched on,

first and second secondary windings that are wound with opposite polarity windings and are coupled to each other at a junction point of like polarity,

output DC voltage source means coupled to said junction point of said first and second secondary windings,

a common series current path coupled to conduct current through said source-drain paths of said first and fourth transistors during one instance of time and through said source-drain drain paths of said second and third transistors during another instance of time, wherein said series current path comprises coupling means for inductively coupling electric magnetic energy from said series current path to said first and second secondary windings, and

timing control means coupled to the gates of all of said field-effect transistors constructed to supply gating signals to said gates of said transistors for controlling the switching of transistors on and off,

the improvement wherein the coupling means comprises first and second primary windings connected in series with each other so as to form the only elements in said series current path, each of said first and second primary windings being coupled to only one of said first and second secondary windings, and

wherein no shunt current path elements are coupled to said series current path, and said first and second primary windings are wound such that they are of an opposite polarity with respect to each other and are also of opposite polarity with respect to that one of said secondary windings to which each of said respective primary windings is coupled, and wherein said timing control means is constructed to supply said gating signals such that the voltages across all of said source-drain paths are approximately zero whenever any of said switching of said transistors occurs.