System for processing data having different formats

• US 5,132,898 A
• Filed: 12/20/1990
• Issued: 07/21/1992
• Est. Priority Date: 09/30/1987
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Sakamura, Ken, Yoshida, Toyohiko
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US07/631,197
• Time in Patent Office: 579 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/210
• CPC Class Codes: G06F 13/4013 with data re-ordering, e.g. Endian conversion
• CPC Class Codes: G06F 5/00 Methods or arrangements for data conversion without changing the order or content of the data handled
• CPC Class Codes: G06F 7/768 Data position reversal, e.g. bit reversal, byte swapping

Abstract

A data processor that executes arithmetic operations between first and second binary numbers, stored in different registers, of different lengths, with the first number having a byte-length smaller than the register, and the second number having a byte-length equal to the register, by storing the first number so that its lower order bit is justified with the lower order bit of the second number. Additionally, data having different bit and byte polarities are processed by reversing the bit and byte order of the data as required.

Claims

1. A data processor comprising:

a decoding mechanism which decodes an instruction, which includes an op code specifying a byte order reversal operation and outputs byte order reversal control information;

a first register which stores data consisting of a plurality of connected bytes; and

a function unit, coupled to said first register and said decoding mechanism, which executes said byte order reversal operation, according to said byte order reversal control information, on said data stored in said first register and stores resulting byte order reversed data in said first register.

2. A data processor comprising:

a decoding mechanism which decodes an instruction, which includes an op code specifying a bit order reversal operation and outputs bit order reversal control information;

a first register which stores data consisting of a plurality of connected bits; and

a function unit, coupled to said first register and said decoding mechanism, which executes said bit order reversal operation, according to said bit order reversal control information, on said data stored in said first register and stores resulting bit order reversed data in said first register.

3. A data processor comprising:

a decoding mechanism which decodes a first type of instruction, which includes an op code specifying a bit order reversal operation to output bit order reversal control information and which decodes a second type of instruction, which includes an op code specifying a byte order reversal operation, to output byte order reversal control information;

a first register which stores data consisting of a plurality of connected bits; and

a function unit, coupled to said first register and said decoding mechanism, which executes said bit order reversal operation, according to said bit order reversal control information, on said data stored in said first register and stores resulting bit order reversed data in said first register and which executes said byte order reversal operation, according to said byte order reversal control information, on said data stored in said first register and stores resulting byte order reversed data in said first register.

4. In a data processor including first and second N byte registers, having least significant and most significant byte and bit storage locations, a processing unit for processing data transferred from said registers, a method for storing and transferring data to and from said registers comprising the steps of:

storing an M byte first data element in said first register and an L byte second data element in said second register, where L and M may have different values and are less than or equal to N, with the least significant bit of each of said first and second data elements stored in the least significant bit storage location of each respective register, with each register having least significant and most significant byte and bit storage locations, with each bit storage location in the register identified by one of 8N bit position numbers and each byte storage location identified by one of N byte position numbers, with the bit position number 8N identifying the least significant bit storage location and with the byte position number N identifying the least significant byte storage location;

directly transferring, without shifting, said first and second stored data elements to said processing unit with the least significant bits of said first and second transferred data elements being aligned to facilitate direct processing of said data elements without the requirement of shifting or reordering the bits of said data elements regardless of whether L and M are the same.

9. The method of claim 4 further comprising a method for performing a bit operation on data stored in said first register comrising the steps of:

providing an instruction including operand size information specifying the number of bytes in a first word stored in said first register and a bit number specifying the displacement, from the leftmost bit of said first word, of the bit to be operated on;

processing said operand size information and said bit number information to determine the bit position number of the bit storge location of said first register where the bit to be operated on is stored.

10. The method of claim 4 wherein said step of storing comprises the steps of:

reversing the byte order of a selected data word to be stored that does not have a least significant byte as the rightmost byte so that the least significant byte of said selected data word is stored in the least significant byte location of said first register.

11. The method of claim 4 wherein said step of storing comprises the steps of:

reversing the bit order of the bits in a selected data word to be stored that does not have a least significant bit as the rightmost bit of said selected data word so that the least significant bit of said selected data word is stored in the least significant bit location of said first register.

5. A data processor comprising:

a decoding mechanism which decodes an instruction, which includes an op code specifying a byte order reversal operation and outputs byte order reversal control information;

a first register which stores data consisting of a plurality of connected bytes;

a function unit, coupled to said first register and said decoding mechanism, which executes said byte order reversal operation, according to said control information, on said data stored in said first register and stores resulting byte reversed data in said first register; and

a second register and where said byte reversed data is stored in said second register by said functional unit.

6. A data processor comprising:

a decoding mechanism which decodes an instruction, which includes an op code specifying a bit order reversal operation and outputs bit order reversal control information;

a first register which stores data consisting of a plurality of connected bits;

a function unit, coupled to said first register and said decoding mechanism, which executes said bit order reversal operation, according to said control information, on said data stored in said first register and stores resulting bit reversed data in said first register; and

a second register and where said bit reversed data is stored in said second register by said functional unit.

7. A data processor comprising:

a decoding mechanism which decodes a first type of instruction, which includes an op code specifying a bit order reversal operation to output bit order reversal control information and which decodes a second type of instruction, which includes an op code specifying a byte order reversal operation, to output byte order reversal control information;

a first register which stores data consisting of a plurality of connected bits;

a function unit, coupled to said first register and said decoding mechanism, which executes said bit order reversal operation, according to said bit order reversal control information, on said data stored in said first register and stores resulting bit reversed data in said first register and which executes said byte reversal operation, according to said byte order reversal control information, on said data stored in said first register and stores resulting byte reversed data in said first register; and

a second register and where said bit reversed or byte reversed data is stored in said second register by said functional unit.

8. The data processor of claim 7 where said instruction includes an operation designation which is decoded by said instruction decoding mechanism to provide an operation indication specifying an operation to be performed on the bit specified by said bit number indication and further comprising:

logic means, that receive said determined register bit position number, for generating and storing a logical data element having all bits equal to a same value except the bit indicated by said bit number indication, where said data element stored in said register and said logical data element are processed to effect said specified operation on the specified bit number of said operand.

12. In a data processor including first and second N byte registers, with each register having least significant and most significant byte and bit storage locations, with each bit storage location in the register identified by one of 8N bit position numbers and each byte storage location identified by one of N byte position numbers, with the bit position number 8N identifying the least significant bit storage location and with byte position number N identifying the least significant byte storage location and with the data processor also including a processing unit for processing data transferred from said registers, a system for storing and transferring data to and from said registers comprising:

means for storing an M byte first data element in said first register and an L byte second data element in said second register, where L and M may have different values and are less than or equal to N, with the least significant bit of each of said first and second data elements stored in the least significant bit storage location of each respective register; and

means for directly transferring, without shifting, said first and second stored data elements to said processing unit with the least significant bits of said first and second transferred data elements being aligned to facilitate direct arithmetic processing of said data elements without the requirement of shifting or reordering the bits of said data elements regardless of whether L and M are the same.

13. The system of claim 12 further comprising a system for performing a bit operation on data stored in said first register by executing a bit instruction including operand size information specifying the number of bytes in a first word stored in said first register and a bit number specifying the displacement from a leftmost boundary bit of said first word of the bit to be operated on, said system comprising:

means for processing said operand size information and said bit number information to determine the bit position number of the bit storage location of said first register where the bit to be operated on is stored.

14. The system of claim 12 wherein said means for storing comprises:

a byte reverse circuit for reversing the byte order of a selected data word that does not have a least significant byte as the rightmost byte to store the least significant byte of said selected data word in the least significant byte location of said first register.

15. The system of claim 12 wherein said means for storing comprises:

a bit reverse circuit for reversing the bit order of a selected data word that does not have a least significant bit as the rightmost bit of selected data word so that the least significant bit of said selected data word is stored in the least significant bit location of said first register.

16. In a data processor including a first N byte register, having least significant and most significant byte and bit storage locations, and a processing unit for processing data transferred from said register, a method for storing and transferring data to and from said register and for performing a bit operation on data stored in said first register comprising the steps of:

storing an M byte first data element in said first register where M is less than or equal to N, with the least significant bit of said first data element stored in the least significant bit storage location of said first register, with said first register having least significant and most significant byte and bit storage locations, with each bit storage location in the register identified by one of 8N bit position numbers and each byte storage location identified by one of N byte position numbers, with the bit position number 8N identifying the least significant bit storage location and with the byte position number N identifying the least significant byte storage location;

directly transferring, without shifting, said first stored data element to said processing unit with the least significant bits of said first transferred data element being aligned to facilitate direct processing of said data element without the requirement of shifting or reordering the bits of said data element;

providing and instruction including operand size information specifying the number of bytes in a first word stored in said first register and a bit number specifying the displacement, from the leftmost bit of said first word, of the bit to be operated on;

processing said operand size information and said bit number information to determine the bit position number of the bit storage location of said first register where the bit to be operated on is stored.

17. In a data processor including a first N byte register, with said first register having least significant and most significant byte and bit storage locations, with each bit storage location in the register identified by one of 8N position numbers and each byte storage location identified by one of N byte position numbers, with the bit position number 8N identifying the least significant bit storage location and with byte position number N identifying the least significant byte storage location and with the data processor also including a processing unit for processing data transferred from said registers, a system for storing and transferring data to and from said register and for performing a bit operation on data stored in said first register by executing a bit instruction including operand size information specifying the number of bytes in a first word stored in said first register and a bit number specifying the displacement from a leftmost boundary bit of said first word of the bit to be operated on, said system comprising:

means for storing an M byte first data element in said first register, where M is less than or equal to N, with the least significant bit of each of said first data element stored in the least significant bit storage location of said first register;

means for directly transferring, without shifting, said first stored data element to said processing unit with the least significant bits of said first transferred data element being aligned to facilitate direct arithmetic processing of said data element without the requirement of shifting or reordering the bits of said data element; and

means for processing said operand size information and said bit number information to determine the bit position number of the bit storage location of said first register where the bit to be operated on is stored.

18. In a data processor including a first N byte register, having least significant and most significant byte and bit storage locations, and a processing unit for processing data transferred from said register, method for storing and transferring data to and from said register comprising the steps of:

storing an M byte first data element in said first register and M is less than or equal to N, with the least significant bit of said first data element stored in the least significant bit storage location of said first register, with said first register having least significant and most significant byte and bit storage locations, with each bit storage location in the register identified by one of 8N bit position numbers and each byte storage location identified by one of N byte position numbers, with the bit position number 8N identifying the least significant bit storage location and with the byte position number N identifying the least significant byte storage location;

directly transferring, without shifting, said first stored data element to said processing unit with the least significant bits of said first transferred data element being aligned to facilitate direct processing of said data element without the requirement of shifting or reordering the bits of said data element; and

reversing the byte order of a selected data word to be stored that does not have a least significant byte as the rightmost byte so that the least significant byte of said selected data word is stored in the least significant byte location of said first register.

19. In a data processor including a first N byte register, with said first register having least significant and most significant byte and bit storage locations, with each bit storage location in the register identified by one of 8N bit position numbers and each byte storage location identified by one of N byte position numbers, with the bit position number 8N identifying the least significant bit storage location and with byte position number N identifying the least significant byte storage location and with the data processor also including a processing unit for processing data transferred from said registers, a system for storing and transferring data to and from said register, said system comprising:

means for storing an M byte first data element in said first register, where M is less than or equal to N, with the least significant bit of each of said first data element stored in the least significant bit storage location of said first register;

means for directly transferring, without shifting, said first stored data element to said processing unit with the least significant bits of said first transferred data element being aligned to facilitate direct arithmetic processing of said data element without the requirement of shifting or reordering the bits of said data elements; and

a byte reverse circuit for reversing the byte order of a selected data word not having the having a least significant byte as the rightmost byte to store the least significant byte of said selected data word in the least significant byte location of said first register.

20. In a data processor including a first N byte register, having least significant and most significant byte and bit storage locations, and a processing unit for processing data transferred from said register, a method for storing and transferring data to and from said register comprising the steps of:

storing an M byte first data element in said first register and M is less than or equal to N, with the least significant bit of said first data element stored in the least significant bit storage location of said first register, with said first register having least significant and most significant byte and bit storage locations, with each bit storage location in the register identified by one of 8N bit position numbers and each byte storage location identified by one of N byte position numbers, with the bit position number 8N identifying the least significant bit storage location and with the byte position number N identifying the least significant byte storage location;

directly transferring, without shifting, said first stored data element to said processing unit with the least significant bits of said first transferred data element being aligned to facilitate direct processing of said data element without the requirement of shifting or reordering the bits of said data element;

reversing the bit order of the bits in a selected data word to be stored that does not have a least significant bit as the rightmost bit of said selected data word so that the least significant bit of said selected data word is stored in the least significant bit location of said first register.

21. In a data processor including a first N byte register, with said first register having least significant and most significant byte and bit storage locations, with each bit storage location in the register identified by one of 8N bit position numbers and each byte storage location identified by one of N byte position numbers, with the bit position number 8N identifying the least significant bit storage location and with byte position number N identifying the least significant byte storage location and with the data processor also including a processing unit for processing data transferred from said registers, a system for storing and transferring data to and from said register, said system comprising:

means for storing an M byte first data element in said first register, where M is less than or equal to N, with the least significant bit of each of said first data element stored in the least significant bit storage location of said first register;

means for directly transferring, without shifting, said first stored data element to said processing unit with the least significant bits of said first transferred data element being aligned to facilitate direct arithmetic processing of said data element without the requirement of shifting or reordering the bits of said data element; and

a bit reverse circuit for reversing the bit order of a selected data word that does not have a least significant bit as the rightmost bit of selected data word so that the least significant bit of said selected data word is stored in the least significant bit location of said first register.