Bit rate adaptation circuit arrangement comprising a justification decision circuit

• US 5,132,970 A
• Filed: 07/06/1990
• Issued: 07/21/1992
• Est. Priority Date: 07/12/1989
• Status: Expired due to Term

• Current Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Urbansky, Ralph
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US07/549,345
• Time in Patent Office: 746 Days
• Field of Search: 370/102, 375/111, 375/112, 364/200 MS File, 364/900 MS File
• US Class Current: 370/506
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Abstract

A circuit arrangement for adapting the bit rates of two signals includes an elastic store into which the data of the first signal are written in parallel in groups of n bits and from which the data bits of the second signal are read out in parallel. A selection matrix for inserting justification bits in the second signal is connected to the output of the elastic store. Writing into the store is controlled by a write counter and read-out therefrom into the selection matrix is controlled by a read counter. A subtractor forms the difference between the counts. A justification decision circuit, which can be realized all or part in CMOS technology and is capable of bit rates of the order of 140 Mbits per second, is connected to the subtractor and the read counter so as to form a control loop for the elastic store. The justification decision circuit includes a controller which produces an output signal corresponding to a running integrated summation of the differences produced by the subtractor, and a pulse distribution circuit. The output signal of the controller controls the pulse distribution circuit to supply pulses which cause the selection matrix to insert justification bits, and cause the read counter to compensate for a difference in the bit rates of the first and second signals.

Claims

1. A circuit arrangement for adapting the bit rates of two digital signals, comprising an elastic store (4) having an input at which the data of the first signal can be written in parallel in groups of "n" bits (n≧

1) and an output at which the data of the second signal can be read out in parallel;

a selection matrix for inserting justification bits in said second signal and which is connected to the output of the elastic store;

writing of data into the elastic store being controlled by a write counter (12) and reading out of data therefrom being controlled by a read counter (13); and

a subtractor (9) connected to the elastic store for deriving the running difference between the read and write counts during reading and writing of data therein;

characterized in that said adaptation circuit arrangement further comprises;

a justification decision circuit (24) connected to said subtractor (9) and to said read counter (13) so as to form therewith a control loop for the elastic store, said justification decision circuit including a controller (17) and a pulse distribution circuit (19);

said controller (17) comprising adding means (171,

     172) connected to said subtractor (9) for deriving a running integrated sum of the differences produced thereby and a first counter (173) connected to said adding means for counting overflow carries of the integrated sums produced thereby, said first counter (173) supplying output signal to said pulse distribution circuit which signify when justification bits are to be supplied by such circuit to said selection matrix;

said pulse distribution circuit (19) being adapted to initiate at least one of the following operations in response to sync pulses (25) externally supplied thereto;

(a) generate a justification indication bit in response to a present sync pulse if since the last previous sync pulse a carry has occurred at the preset bit position in the output signal produced by said first counter (173);

(b) transmit to said selection matrix (5) a signal which causes it to insert a justification bit;

(c) transmit to said read counter (13) a signal which holds the count therein for one clock period if the number of justification bits inserted prior to a present sync pulse exceeds an integral multiple of "n".

2. A circuit arrangement as claimed in claim 1, characterized in that said adding means comprises an adder (171) and a store (172) connected to said first counter (173) in that order;

said first counter (173) is bidirectional; and

said adder (171) is connected to said subtractor (9) so as to accumulate in said store (172) the integrated sum of the differences formed by said subtractor (9);

said bidirectional first counter (173) receiving an increment pulse from said store (172) when such store has a positive overflow and receiving a decrement pulse therefrom when such store has a negative overflow.

3. A circuit arrangement as claimed in claim 2, further characterized in that said pulse distribution circuit (19) comprises:

a second bidirectional counter (191) for counting the number of carries at said preset bit position in the output signal of said first counter (173), taking into account the sign of such output signal;

a carry store (192) in which the contents of the second bidirectional counter (191) and also the carry pulse itself are stored each time a carry occurs;

a third store (193) into which the carry pulse is transferred from the carry store (192) each time a first sync pulse 25(a) is supplied to said third store (193); and

a buffer (194) into which the remaining contents of the carry store (192) are transferred each time a second sync pulse 25(b) is supplied to said buffer (194).

4. A circuit arrangement as claimed in claim 3, wherein said justification decision circuit further comprises a gate (26) for forming the difference between the binary values of the most significant bit at the input and output of said buffer (194) and supplying such difference as an additional input to said adder (171).