Disk controller includes cache memory and a local processor which limits data transfers from memory to cache in accordance with a maximum look ahead parameter

• US 5,133,060 A
• Filed: 06/05/1989
• Issued: 07/21/1992
• Est. Priority Date: 06/05/1989
• Status: Expired due to Fees

• Current Assignee: PhoneTel Communications Incorporated
• Original Assignee: CompuAdd Corporation (Zeos International Ltd)
• Inventors: Weber, Theodore E., Tischler, Paul V.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Gechil, Mehmet
• Application Number:
  US07/361,227
• Time in Patent Office: 1,142 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/425
• US Class Current: 711/113
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch

Abstract

A controller (10) for use with a hard disk (38) or other mass storage medium provides a memory cache (36). A block descriptor table (40 ) is divided into a plurality of sets (42), depending upon the size of the memory cache (36). Each set is similarly indexed to define memory groups (44) having tag, cache address, and usage information. Upon a read command, an index is generated corresponding to the address requested by the host computer, and the tag information is matched with a generated tag from the address. Each set is checked until a hit occurs or a miss occurs in every set. After each miss, the usage information (50) corresponding to the memory group (44) is decremented. When reading information from the storage device (32) to the memory cache (36), the controller (10) may selectively read additional sectors. The number of sectors read from the storage device may be selectively controlled by the user or the host processor. Further, a cap may be provided to provide a maximum number of sectors to be read.

Claims

1. A controller for transferring data between a host processing unit and a storage device comprising:

a host interface for communicating with the host processing unit, said host interface receiving from the host processing unit one or more look-ahead parameters, one of said look-ahead parameters having a multiplying factor, one of said look-ahead parameters further having a maximum, said host interface further receiving read requests and associated address information including an address indicative of a starting location on said storage device and a first number indicative of a number of memory units to be read from said storage device;

a storage interface for communicating with said storage device;

a cache memory coupled with said host interface and storage interface for storing requested memory units; and

a local processor coupled to the storage interface for initiating a transfer of a number of units from the storage device responsive to the look-ahead parameters to the cache memory, the number of units transferred being dependent upon and greater than said first number, said local processor multiplying said first number by the multiplying the number of memory units to be transferred, and said local processor limits the number of memory units to be transferred responsive to the maximum in said look-ahead parameters.

2. A controller for transferring data between a host processing unit and a storage device comprising:

a host interface for communicating with the host processing unit, said host interface receiving from the host processing unit one or more look-ahead parameters, one of said look-ahead parameters having a multiplying factor, read requests and associated address information including an address indicative of a starting location on said storage device and a first number indicative of a number of memory units to be read from said storage device;

a storage interface for communicating with said storage device;

a cache memory coupled with said host interface and storage interface for storing requested memory units; and

a local processor coupled to the storage interface for initiating a transfer of a number of units from the storage device responsive to the look-ahead parameters to the cache memory, the number of units transferred being dependent upon and greater than said first number, said local processor multiplying said first number by the multiplying the number of memory units to be transferred, and said local processor receiving said multiplying factor during the execution of an application program by the host processing unit, such that the number of transferred memory units can be varied depending upon the nature of the information being read.

3. A controller for transferring data between a host processing unit and a storage device comprising:

a host interface for communicating with the host processing unit, said host interface receiving from the host processing unit one or more look-ahead parameters, one of said look-ahead parameters having a multiplying factor, read requests and associated address information including an address indicative of a starting location on said storage device and a first number indicative of a number of memory units to be read from said storage device;

a storage interface for communicating with said storage device;

a cache memory coupled with said host interface and storage interface for storing requested memory units; and

a local processor coupled to the storage interface for initiating a transfer of a number of units from the storage device responsive to the look-ahead parameters to the cache memory, the number of units transferred being dependent upon and greater than said first number, said local processor multiplying said first number by the multiplying the number of memory units to be transferred, and said local processor multiplying said first number by shifting said first number by a predetermined number of bits to calculate the number of memory units to be transferred, such that said first number is multiplied by a factor of 2ⁿ, where n represents the number of shifts performed on said first number.