Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories
First Claim
1. A split-polysilicon CMOS DRAM process incorporating stacked-capacitor cells, said process commencing with a lightly-doped P-type wafer, and comprising the following sequence of steps:
- (a) creating N-well regions within certain portions of the wafer;
(b) creating P-well regions within other portions of the wafer;
(c) creating channel-stop regions within portions of the wafer above which field oxide regions will be created;
(d) creating said field oxide regions;
(e) depositing a first polysilicon layer on the surface of the wafer;
(f) doping said first polysilicon layer in order to render it conductive;
(g) patterning N-channel FET gates and N-channel interconnects from said first polysilicon layer and creating an unetched expanse of a portion of said first polysilicon layer in P-channel regions;
(h) depositing a first silicon dioxide spacer layer over the surface of the wafer;
(i) performing an unmasked lightly-doped source/drain implant with phosphorus;
(j) depositing a second silicon dioxide spacer layer;
(k) performing a masking step which exposes said second spacer layer superjacent storage-node contact regions;
(l) performing an anisotropic etch which exposes the storage-node contact regions;
(m) deposition of a second polysilicon layer over the surface of the wafer;
(n) doping said second polysilicon layer in order to render it conductive;
(o) patterning of individual storage-node plates from said second polysilicon layer;
(p) depositing a capacitor dielectric layer over the surface of the wafer;
(q) depositing a third polysilicon layer over the surface of the wafer;
(r) doping said third polysilicon layer in order to render it conductive;
(s) patterning said third polysilicon layer to create a cell plate;
(t) performing an anisotropic oxide spacer etch, which creates spacers from said first and second spacer layers on the edges of the N-channel FET gates on either side of the bitline contact regions, and also exposes the bitline contact regions;
(u) performing an unmasked N+ source/drain implant;
(v) patterning P-channel transistors and P-channel interconnects from the unetched expanse of said first polysilicon layer using a mask which defines P-channel gates and interconnects and blankets the N-channel regions;
(w) performing a P-channel source/drain implant prior to the removal of the mask used to pattern P-channel gates and interconnects;
(x) depositing an interlayer dielectric layer;
(y) performing a masking step which exposes portions of the interlayer dielectric layer superjacent bitline contact regions;
(z) opening bitline contact with an anisotropic etch;
(aa) creation of bitlines; and
(bb) depositing at least one passivation layer.
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Abstract
This invention constitutes a 10-12 mask, split-polysilicon process for fabricating dynamic random access memories of the stacked capacitor type for the one-megabit generation and beyond. The process flow is characterized: reduced mask count due to the elimination of the N+ and p+ source-drain masking layers via the split polysilicon technique; an option to further reduce wafer processing by allowing the LOCOS stress relief (pad) oxide layer to later function as the transistor gate dielectric layer; N-channel device optimization via self-aligned punch-through and lightly-doped-drain (LDD) implants, without the addition of extra P-channel masking steps via the split poly approach; use of semi, self-aligned contact of bottom cell plate to access gate diffusion allowing tight spacing between bottom cell plate buried contact and access gate polysilicon; improved refresh characteristics achieved by avoiding reduction of isolation thickness due to the spacer oxide etch; improved refresh characteristics achieved by protecting the sensitive areas of the storage node from damage typically caused by a spacer oxide etch; improved refresh characteristics achieved by eliminating the high-dose N-channel source/drain implantation from the storage node side of the access transistor gate; and improved immunity to soft error upset achieved through the use of an optional self-aligned "Hi-C" implant that is performed without the addition of an extra masking step.
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Citations
23 Claims
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1. A split-polysilicon CMOS DRAM process incorporating stacked-capacitor cells, said process commencing with a lightly-doped P-type wafer, and comprising the following sequence of steps:
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(a) creating N-well regions within certain portions of the wafer; (b) creating P-well regions within other portions of the wafer; (c) creating channel-stop regions within portions of the wafer above which field oxide regions will be created; (d) creating said field oxide regions; (e) depositing a first polysilicon layer on the surface of the wafer; (f) doping said first polysilicon layer in order to render it conductive; (g) patterning N-channel FET gates and N-channel interconnects from said first polysilicon layer and creating an unetched expanse of a portion of said first polysilicon layer in P-channel regions; (h) depositing a first silicon dioxide spacer layer over the surface of the wafer; (i) performing an unmasked lightly-doped source/drain implant with phosphorus; (j) depositing a second silicon dioxide spacer layer; (k) performing a masking step which exposes said second spacer layer superjacent storage-node contact regions; (l) performing an anisotropic etch which exposes the storage-node contact regions; (m) deposition of a second polysilicon layer over the surface of the wafer; (n) doping said second polysilicon layer in order to render it conductive; (o) patterning of individual storage-node plates from said second polysilicon layer; (p) depositing a capacitor dielectric layer over the surface of the wafer; (q) depositing a third polysilicon layer over the surface of the wafer; (r) doping said third polysilicon layer in order to render it conductive; (s) patterning said third polysilicon layer to create a cell plate; (t) performing an anisotropic oxide spacer etch, which creates spacers from said first and second spacer layers on the edges of the N-channel FET gates on either side of the bitline contact regions, and also exposes the bitline contact regions; (u) performing an unmasked N+ source/drain implant; (v) patterning P-channel transistors and P-channel interconnects from the unetched expanse of said first polysilicon layer using a mask which defines P-channel gates and interconnects and blankets the N-channel regions; (w) performing a P-channel source/drain implant prior to the removal of the mask used to pattern P-channel gates and interconnects; (x) depositing an interlayer dielectric layer; (y) performing a masking step which exposes portions of the interlayer dielectric layer superjacent bitline contact regions; (z) opening bitline contact with an anisotropic etch; (aa) creation of bitlines; and (bb) depositing at least one passivation layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A split-polysilicon CMOS DRAM process incorporating stacked-capacitor cells, said process commencing with a lightly-doped P-type wafer, and comprising the following sequence of steps:
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(a) creating N-well regions within certain portions of the wafer; (b) creating P-well regions within outer portions of the wafer; (c) creating channel-stop regions within portions of the wafer above which device isolation regions will be created; (d) creating said device isolation regions; (e) creating a first conductive layer, which blankets the wafer'"'"'s surface; (f) patterning N-channel FET gates and N-channel interconnects from said first conductive layer and creating an expanse of unetched first conductive layer material in P-channel regions; (g) depositing at least one dielectric spacer layer, which blankets the wafer'"'"'s surface; (h) performing a masking step which exposes portions of the spacer layer superjacent storage-node contact regions; (i) performing an anisotropic etch which exposes the storage-node contact regions; (j) creating a second conductive layer, which blankets the wafer'"'"'s surface; (k) patterning individual storage-node plates from said second polysilicon layer; (l) creating a capacitor dielectric layer; (m) creating a third conductive layer; (n) patterning the third conductive layer to create a cell plate; (o) performing an anisotropic oxide spacer etch, which creates spacers from said first and second dielectric spacer layers on the edges of the N-channel FET gates on either side of the bitline contact regions, and also exposes the bitline contact regions; (p) performing an unmasked N+ source/drain implant; (g) patterning P-channel FET gates and P-channel interconnects from the unetched expanse of said first conductive layer using a mask which defines P-channel gates and interconnects and blankets the N-channel regions; (r) performing a P-channel source/drain implant prior to the removal of the photoresist mask used to pattern P-channel gates and interconnects; (s) depositing an interlayer dielectric layer; (t) performing a masking step which exposes portions of the interlayer dielectric lay superjacent bitline contact regions; (u) creating bitline contact openings with an anisotropic etch; (v) creation of bitlines; and (w) deposition of at least one passivation layer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification