MOSFET with substrate source contact

• US 5,134,448 A
• Filed: 01/22/1991
• Issued: 07/28/1992
• Est. Priority Date: 01/29/1990
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Sanders, Paul W., Johnsen, Robert J.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/643,636
• Time in Patent Office: 553 Days
• Field of Search: 357/23.4, 357/41, 437/913
• US Class Current: 257/330
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N⁺, N-, P-, N⁺ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N⁺ interface. A buried P-, N⁺ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N⁺ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.

Claims

1. A vertical MOSFET device comprising:

a semiconductor substrate having first and second opposed surfaces;

a drain region adjacent the first surface, a channel forming region underlying the drain region, a source region underlying the channel forming region and a gate dielectric and electrode on a portion of the channel forming region between the source and drain regions for modulating the conductivity therebetween; and

a buried ohmic contact shorting part of the channel forming region to the underlying source region.

2. The device of claim 1 wherein the buried ohmic contact is formed in a cavity extending from the first surface into the substrate and having a sidewall portion which is inclined so that a PN junction between the channel forming region and the source may be viewed when looking into the cavity.

3. The device of claim 1 further comprising a drift region between the channel forming region and the drain region.

4. The device of claim 1 further comprising a source contact extending to the second surface and a drain contact extending to the first surface.

5. The device of claim 1 wherein the buried ohmic contact is formed in a first cavity extending from the first surface into the substrate.

6. The device of claim 5 wherein the gate dielectric and electrode are formed on the sidewalls of a second cavity extending from the first surface into the substrate.

7. A semiconductor device comprising:

a semiconductor substrate having first and second opposed principal surfaces;

a vertical MOSFET in the substrate, having source, drain, and gate for forming a channel permitting current flow between a source contact on the second surface and a drain contact on the first surface; and

a buried ohmic contact within the substrate shorting the source to part of an internal region of the substrate in which the channel is formed.

8. The semiconductor device of claim 7 wherein the vertical MOSFET is formed in a first cavity extending from the first surface into the substrate.

9. The semiconductor device of claim 8 wherein the buried ohmic contact is formed in a second cavity extending from the first surface into the substrate.

10. A semiconductor device comprising:

a first semiconductor region of a first conductivity and type;

a second semiconductor region on the first semiconductor region and of a second conductivity and of a second type opposite the first type;

a third semiconductor region on the second semiconductor region and of a third conductivity and of the first type;

a fourth semiconductor region in the third semiconductor region and of a fourth conductivity and of the first type and extending to an upper surface of the third region;

a first cavity having first and second sidewalls extending from the upper surface to the first region, wherein portions of the first and second regions are exposed in the first cavity;

a first dielectric on a first portion of the second region exposed in the first cavity;

a conductor on a first portion of the first region and a second portion of the second region exposed in the first cavity and ohmically contacting the first and second regions but not the third region; and

a gate electrode on a second dielectric formed on the sidewalls of a second cavity extending from the upper surface to the first region, a source electrode contacting the first region and a drain electrode contacting the fourth region.

11. The device of claim 10 wherein the second cavity has a "V" shaped bottom.