MOS semiconductive device

• US 5,134,451 A
• Filed: 04/13/1990
• Issued: 07/28/1992
• Est. Priority Date: 04/17/1989
• Status: Expired due to Term

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Katoh, Teruo
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Ho, Tan
• Application Number:
  US07/509,478
• Time in Patent Office: 837 Days
• Field of Search: 357/23.15, 357/67 S, 357/56, 357/71 S, 357/23.1
• US Class Current: 257/384
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A semiconductive device which comprises a gate insulating film composed of a metal oxide film, source/drain electrodes, and metal silicide layers formed on the source/drain regions is described.

Claims

1. A semiconductor device comprising:

a substrate having a first conductivity type;

a source region and a drain region, each having a second conductivity type, separately disposed within a surface of said substrate, said source and drain regions defining a channel region therebetween;

a single layer, comprising a metal material, extending over said substrate;

said single layer having first and second metal silicide portions covering said source region and drain region, and a metal oxide portion extending over said channel region; and

a gate electrode extending over said metal oxide portion.

2. The device according to claim 1, further comprising a thin insulating layer covering said channel region, wherein said metal oxide portion covers said insulating layer;

said thin insulating layer and metal oxide portion thereby forming a composite gate insulator.

3. The device according to claim 2, wherein said first and second metal silicide portions comprise tantalum silicide and wherein said metal oxide portion comprises tantalum oxide.

4. The device according to claim 3, wherein said thin insulating layer comprises a silicon oxide layer, said silicon oxide layer being formed in coincidence with said metal oxide portion.

5. The device of claim 1 wherein said single layer is continuous between said metal silicide portions.

6. A semiconductor device comprising:

a substrate having a major surface;

a gate electrode extending over a first portion in said major surface of said substrate;

a single layer, comprising a metal material, extending over said major surface and gate electrode;

said single layer having first and second metal silicide portions respectively extending over corresponding second and third portions in said major surface of said substrate, said second and third portions defining said first portion therebetween; and

a metal oxide portion established on said gate electrode;

a silicon material layer, established on said single layer, covering said first and second metal silicide portions and said metal oxide portion, said silicon material layer including source and drain regions therein each doped with a predetermined impurity and disposed on said first and second metal silicide portions, said silicon material layer further including a channel region therein disposed on said metal oxide portion.

7. The device according to claim 6, wherein said first and second metal silicide portions comprises a tantalum silicide portion and wherein said metal oxide layer comprises tantalum oxide.

8. The device according to claim 6, wherein said major surface of said substrate is covered with a thin insulating layer and wherein said gate electrode and said first and second metal silicide portion of said single layer cover said thin insulating layer.

9. The device according to claim 6 wherein said single layer is continuous between said metal silicide portions.

10. A semiconductor device of the type having a substrate having a first conductivity type, a source region and a drain region, each having a second conductivity type, the source and drain regions being spaced apart and located within a surface of said substrate to define a channel region therebetween, and a gate electrode located over the channel, further comprising:

a single layer comprising a metal material extending over said substrate, said single layer consisting essentially of first and second metal silicide portions covering said source region and drain region, and a metal oxide portion extending over said channel region; and

wherein said gate electrode extends over said metal oxide portion.

11. The device of claim 10 wherein said single layer is continuous between said metal silicide portions.