Field effect device with polycrystalline silicon channel
First Claim
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1. A method for fabricating a load element for a CMOS SRAM memory cell, comprising the steps of:
- forming an n-channel field effect device in a semiconductor substrate, such field effect device having source/drain regions opposite a gate electrode and a channel under the gate electrode within the substrate;
forming a gate oxide layer over the substrate;
forming an opening through the gate oxide layer to expose an underlying conductive region;
forming a layer of polycrystalline silicon over the gate oxide layer and the exposed underlying conductive region;
forming p-type source/drain regions in the polycrystalline silicon layer;
forming a p-channel region in the polycrystalline silicon layer between the p-type source/drain regions; and
etching portions of the polycrystalline silicon layer to define an elongate p-channel element connecting the p-type source/drain regions, such element having a length substantially longer than a width of the element.
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Abstract
A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SPRAM cells.
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10 Claims
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1. A method for fabricating a load element for a CMOS SRAM memory cell, comprising the steps of:
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forming an n-channel field effect device in a semiconductor substrate, such field effect device having source/drain regions opposite a gate electrode and a channel under the gate electrode within the substrate; forming a gate oxide layer over the substrate; forming an opening through the gate oxide layer to expose an underlying conductive region; forming a layer of polycrystalline silicon over the gate oxide layer and the exposed underlying conductive region; forming p-type source/drain regions in the polycrystalline silicon layer; forming a p-channel region in the polycrystalline silicon layer between the p-type source/drain regions; and etching portions of the polycrystalline silicon layer to define an elongate p-channel element connecting the p-type source/drain regions, such element having a length substantially longer than a width of the element. - View Dependent Claims (2, 3, 5, 6, 7, 8, 9, 10)
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4. A method for fabricating a CMOS SRAM cell, comprising the steps of:
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forming two n-channel transistors in a semiconductor substrate, such transistors each having two source/drain regions separated by a channel region and having a gate electrode disposed over the channel region, wherein a first source/drain region of each n-channel transistor is common with the other; forming a gate oxide layer over the substrate and the gate electrodes; forming openings in the gate oxide layer to expose portions of each gate electrode and a second source/drain region of each n-channel transistor; forming a layer of polycrystalline silicon over the gate oxide layer and filling the opening; forming alternating p-type and n-type conductive regions within the polycrystalline silicon layer; and etching said polycrystalline silicon layer to form two elongate structures, each elongate structure having two ends and a p-channel region between them overlying the second source/drain region of one of the n-channel transistors so that such second source/drain regions function as gate electrodes for the p-channel regions, wherein the elongate structures each connect to power lines at one end and to both a gate of one of the n-channel transistors and the second source/drain region of the other n-channel transistor at the other to form a cross-coupled latch.
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