Glitch free power-up for a programmable array

• US 5,136,186 A
• Filed: 08/30/1991
• Issued: 08/04/1992
• Est. Priority Date: 08/30/1991
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: Waferscale Integration, Inc. (STMicroelectronics NV)
• Inventors: Trinh, Cuong, Shubat, Alex
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US07/752,733
• Time in Patent Office: 340 Days
• Field of Search: 307/443, 307/465, 307/542, 307/557, 307/241, 307/242, 307/572
• US Class Current: 327/142
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/17708 using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
• CPC Class Codes: H03K 19/17712 one of the matrices at least being reprogrammable

Abstract

Dummy circuitry, including a dummy input buffer, associated lines, and an additional row in the PLD array, provides an additional input to the PLD to keep the voltage on the bit line low until the correct input signal has fully propagated through the working input buffer and associated lines, thereby preventing a voltage glitch.

Claims

1. Structure comprising:

a signal line connected to a circuit for driving said circuit;

a first plurality of storage elements connected to said signal line;

means for clamping said signal line at a first specified signal level for a selected time during power-down of said structure; and

means for maintaining said signal line at a predetermined signal range for a selected time during power-up of said structure to prevent said signal line from developing a voltage glitch during power-up.

2. Structure as in claim 1 wherein said means for maintaining said signal line at said predetermined signal range comprises a dummy circuit connected to said signal line.

3. Structure as in claim 2 wherein said dummy circuit is deactivated after all said first plurality of storage elements have been activated during power-up.

4. Structure as in claim 2 wherein each of said first plurality of storage elements comprises an input line;

wherein said dummy circuit comprises an input line;

wherein said input line of said dummy circuit is positioned relative to one of said input lines of said first plurality of storage elements such that said dummy circuit is deactivated after all said first plurality of storage elements have been activated during power-up.

5. Structure as in claim 2 wherein said predetermined signal range is achieved by said dummy circuit overriding said first plurality of storage elements to provide said specified signal level.

6. Structure as in claim 5 wherein said predetermined signal range is between said first specified signal level and a second specified signal level.

7. Structure as in claim 6 wherein said second specified signal level is a maximum value which is a trip point of said circuit.

8. Structure as in claim 7 wherein said circuit is a sense amplifier.

9. Structure of claim 7 wherein said dummy circuit comprises a second plurality of storage elements, each of said second plurality of storage elements having a substantially similar configuration to said first plurality of storage elements.

10. Structure as in claim 1 wherein said means for maintaining is positioned relative to said first plurality of storage elements such that said means for maintaining is deactivated after all said plurality of storage elements have been activated during power-up.

11. Structure comprising:

a signal line connected to a circuit for driving said circuit;

a first plurality of storage elements connected to said signal line;

means for clamping said signal line at a first specified signal level for a selected time during power down of said structure; and

a second plurality of storage elements for maintaining said signal line at a predetermined signal range for a selected time during power-up of said structure to prevent said signal line from developing a voltage glitch during power-up.

12. Structure as in claim 11 wherein said second plurality of storage elements are connected to said signal line.

13. Structure as in claim 12 wherein said second plurality of storage elements are deactivated after all said first plurality of storage elements have been activated during power-up.

14. Structure as in claim 12 wherein each of said first plurality of storage elements comprises an input line;

wherein each of said second plurality of storage elements comprises an input line;

wherein said input lines of said second plurality of storage elements are positioned relative to said input lines of said first plurality of storage elements such that said second plurality of storage elements are activated after all said first plurality of storage elements have been activated during power-up.

15. Structure as in claim 12 wherein said predetermined signal range is achieved by said second plurality of storage elements overriding said first plurality of storage elements to provide said predetermined signal range.

16. Structure as in claim 15 wherein said predetermined signal range is between said first specified signal level and a second specified signal level.

17. Structure as in claim 16 wherein said second specified signal level is a maximum value which is a trip point of said circuit.

18. Structure as in claim 17 wherein said circuit is a sense amplifier.

19. Structure of claim 17 wherein said second plurality of storage elements have a substantially similarly configuration to said first plurality of storage elements.