PLL clock synthesizer using current controlled ring oscillator

• US 5,136,260 A
• Filed: 03/08/1991
• Issued: 08/04/1992
• Est. Priority Date: 03/08/1991
• Status: Expired due to Term

• Current Assignee: Western Digital Corporation
• Original Assignee: Western Digital Corporation
• Inventors: Yousefi-Elezei, Nariman
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US07/666,224
• Time in Patent Office: 515 Days
• Field of Search: 331/17, 331/25, 331/34, 331/57, 307/602, 307/603, 307/605
• US Class Current: 331/17
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A high frequency clock signal synthesizer circuit employs a single fixed reference clock signal to generate one or more variable frequency clock signals. A phase comparator and a variable count counter generate a control signal from the reference clock and circuit output and provide it to a voltage controlled oscillator. High frequency stability of the voltage controlled oscillator is provided by a ring oscillator with a control signal response which is linear even at high frequencies. The ring oscillator employs an odd number of inverting delay stages coupled in series in a ring configuration, each delay stage having an input, an output, an inverter coupled to the input and a controllable current source buffering the switching transistors of the inverter from the output. A bias circuit controls the current of the current source and thereby controls the delay of each delay stage and thus the frequency of the ring oscillator. The buffering of the switching transistors from the output nodes of the delay stages prevents transient effects due to parasitic capacitances and process variations from affecting the current to the output node and hence from affecting the delay of the delay stage and the frequency of the ring oscillator.

Claims

1. A high frequency clock signal synthesizer circuit, comprising:

a source of periodic reference signal;

phase comparison means receiving said reference signal as a first input signal and receiving a second input signal, said phase comparison means comparing the phase between the two input signals and providing a first output when the first input signal leads the second input signal in phase and a second output when the first input frequency lags the second input frequency in phase;

means, coupled to the phase comparison means, for receiving the first output signal and the second output signal and providing a first control current derived from the first output signal and the second output signal;

means for receiving the first control current and converting the first control current to a control voltage;

voltage to current conversion means, coupled to the means for providing a control voltage, for receiving the control voltage and providing a second control current corresponding thereto;

ring oscillator means, coupled to the voltage to current conversion means, for receiving the second control current and providing a high frequency output signal having a frequency determined by said second control current, said ring oscillator means including an odd number of inverting delay stages and means for buffering the output thereof from transient switching characteristics to provide a substantially linear frequency response characteristic to the control current;

means for receiving said high frequency output signal and providing a variable lower frequency signal derived from said output signal as said second input signal; and

means, coupled to said means for providing said second input signal, for controlling the variable frequency of said second input signal.

2. A circuit as set out in claim 1, wherein said ring oscillator means further comprises a bias means for receiving the second control current and biasing the buffer means of each inverting delay stage so as to mirror the second control current therethrough.

3. A circuit as set out in claim 2, wherein each of said delay stages further comprises one or more switching transistors and wherein said bias means includes a load transistor matching the load characteristics of said switching transistors.

4. A circuit as set out in claim 1, wherein said means for providing the variable frequency second input signal comprises a variable value counter, and wherein said means for controlling determines the value of the counter.

5. A ring oscillator circuit, comprising:

a plurality of delay stages coupled in series in a ring configuration, each delay stage comprising;

an input node;

an output node;

an inverter coupled to the input node and including a switching field effect transistor coupled between a first reference voltage and a second reference voltage; and

a controllable current source including a field effect transistor coupled between the switching transistor and the output node;

wherein the plurality of delay stages are coupled together such that the output node of the last of the delay stages is coupled to the input node of the first of the delay stages; and

bias means for providing a control signal to the gate of said current source field effect transistor in each of said plurality of delay stages to adjust the current through said current source field effect transistor, wherein said bias means includes a first bias transistor and a second bias transistor, having the same conductivity type as said switching field effect transistor and said current source transistor, respectively, and having matching load characteristics therewith.

6. A ring oscillator circuit, comprising:

a plurality of delay stages coupled in series in a ring configuration, each delay stage comprising;

an input node;

an output node;

an inverter coupled to the input node and including a first switching field effect transistor coupled to a first reference voltage and having the input node coupled to the gate thereof and a second switching field effect transistor coupled to a second reference voltage source and having an opposite conductivity type to said first switching transistor and having the input node coupled to the gate thereof; and

a controllable current source including a first current supply field effect transistor having the same conductivity type as said first switching transistor and coupled between the first switching transistor and the output node and a second current source transistor having the same conductivity type as said second switching transistor and coupled between the second switching transistor and the output node;

wherein the plurality of delay stages are coupled together such that the output node of the last of the delay stages is coupled to the input node of the first of the delay stages; and

bias means for providing a control signal to the gate of said current source field effect transistor in each of said plurality of delay stages to adjust the current through said current source field effect transistor, wherein said bias means comprises a first bias circuit having a first bias transistor matching the first switching transistor in load characteristics and conductivity type and a second bias transistor matching the first current source transistor in load characteristics and conductivity type, and a second bias circuit including a third bias transistor matching the second switching transistor in load characteristics and conductivity type and a fourth bias transistor matching the second current source transistor in load characteristics and conductivity type.

7. A CMOS delay circuit, adapted to impart a variable delay to an input signal, comprising:

an input node for receiving the input signal;

an output node;

a CMOS inverter including a p-channel field effect transistor and an n-channel field effect transistor coupled between a positive voltage source and ground wherein the p-channel and n-channel transistors receive the input signal at the gates thereof and provide an inverted signal to said output node;

a p-channel buffer transistor coupled between the p-channel inverter transistor and the output node;

an n-channel buffer transistor coupled between the inverting n-channel inverter transistor and the output node; and

a bias means for providing a bias signal to said buffer transistors to control the current provided thereby and thereby control the delay of said delay circuit, said bias means including a first load matching the on resistance of the p-channel switching transistor and a second load matching the on resistance of the n-channel switching transistor.