Hardware interface for high speed video imaging

• US 5,136,383 A
• Filed: 03/28/1991
• Issued: 08/04/1992
• Est. Priority Date: 03/28/1991
• Status: Expired due to Fees

• Current Assignee: United States Of America As Represented By The Secretary Of The Army (Government of the United States of America)
• Original Assignee: The United States Of America As Represented By The Secretary Of The Army
• Inventors: Shepard, Steven M., Sass, David T.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Metjahic, Safet
• Application Number:
  US07/676,669
• Time in Patent Office: 495 Days
• Field of Search: 358/160, 358/111, 358/110, 358/21 R, 358/113, 358/93, 358/148, 358/107, 358/209, 358/108, 358/208, 358/206, 358/225, 358/903, 358/213.13, 358/149, 358/153, 358/154 581
• US Class Current: 348/500
• CPC Class Codes: H04N 5/04 Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/30 Transforming light or analogous information into electric information scanning details H04N3/00; cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00; circuitry of solid-state image sensors [SSIS] or control thereof H04N25/00
• CPC Class Codes: H04N 5/4448 for frame-grabbing
• CPC Class Codes: H04N 7/002 Special television systems not provided for by H04N7/007 - H04N7/18 still pictures via a television channel H04N1/00098
• CPC Class Codes: H04N 7/188 Capturing isolated or intermittent images triggered by the occurrence of a predetermined event, e.g. an object reaching a predetermined position signal generation from motion picture films H04N5/253

Abstract

The invention is synchronization hardware for assisting the processing of video signals in a high speed imaging system, the hardware having logic circuitry for selecting acceptable pictoral units from within frames of a video signal. The synchronization hardware also has circuits for electronically coordinating a camera, a frame grabber, a host computer for the frame grabber and a flagging signal generator.

Claims

1. Synchronization hardware for an imaging system wherein the imaging system includes a camera whose video signal represents pictoral units grouped in frames and signal subcomponents separating the frames;

the system further including a frame grabber receiving the video signal from the camera, a host computer communicating with the frame grabber, and a flagging signal generator communicating with the hardware;

the synchronization hardware comprising;

counting circuitry receiving the video signal and counting the pictoral units within the frames, the counting circuitry assigning sequential numbers to the pictoral units;

the counting circuitry having restart means for reinitializing the counting circuitry at each occurrence of the signal subcomponents;

latch means for receiving the sequential numbers, latching selected sequential numbers and causing the frame grabber to save representations of pictoral units associated with the selected sequential numbers;

a set of latches within the latch means;

a shift register connected to and controlling the latches;

first logic circuitry sending a first logic signal when the frame grabber can accept the sequential numbers and the associated pictoral units, the first logic circuitry sending a second logic signal when the frame grabber can not accept the sequential numbers and the associated pictoral units;

the first logic circuitry being connected to the counting circuitry, the shift register and the host computer;

the first logic circuitry sending the first or second logic signal in response to inputs from the counting circuitry, the shift register and the host computer;

aperture adjust circuitry for converting feedback signals from the camera to an aperture signal occurring once per each pictoral unit, the aperture adjust circuitry including a manually operable means for adjusting the phase relation between the aperture signal and the video signal;

the aperture adjust circuitry further including manually adjustable means for controlling width of the aperture signal;

outputting circuitry for outputting third logic signals in response to flagging signals, the outputting circuitry including manually operable means for controlling a time delay between receipt of one of the flagging signals and output of a corresponding second logic signal;

second logic circuitry connected to the first logic circuitry, the aperture adjust circuitry and the outputting circuitry;

the second logic circuitry sending a pulse to the shift register at concurrence of one of the aperture signals, one of the third logic signals and one of the first logic signals.

2. The hardware of claim 1 wherein the second logic circuitry is comprised of:

a first AND gate receiving aperture signals from the aperture adjust circuitry;

a second AND gate receiving the third logic signals from the outputting circuitry and receiving first logic signals from the first logic circuitry;

a first flip-flop connected to the AND gates and receiving AND gate signals from the AND gates.

3. The hadware of claim 2 wherein the first flip flop is connected to and sends a control signal to the shift register and a one shot circuit, the one shot circuit having means to clear the first flip-flop so that the control signal is truncated to become a control pulse.

4. The hardware of claim 3 wherein the shift register is comprised of:

a series of cascaded flip-flops, each of the cascaded flip-flops being connected to one of the latches;

a first connector accepting reset signals from the host computer and sending the reset signals simultaneously to each of the cascaded flip-flops;

a second connector accepting control pulses from the second logic circuitry and sending the control pulses simultaneously to each of the cascaded flip-flops;

5. Hardware connecting components of an imaging system wherein the system includes a camera whose video signal represents pictoral units grouped in frames and signal subcomponents separating the frames;

the system further including a frame grabber receiving the video signal, a computer communicating with the frame grabber, and a flagging signal generator communicating with the hardware;

the hardware comprising;

counting circuitry receiving the video signal and counting the pictoral units within the frames;

a latch means for receiving count numbers from the counting circuitry, latching selected count numbers and causing the frame grabber to save pictoral units associated with the selected count numbers;

first logic circuitry sending a first logic signal when the frame grabber can accept the count numbers and the associated pictoral units, the first logic circuitry being connected to and responding to the counting circuitry, the latch means and the computer;

aperture adjust circuitry converting feedback signals from the camera to aperture signals, the aperture adjust circuitry including a manually operable means for adjusting the aperture signals;

outputting circuitry for outputting second logic signals in response to the flagging signals, the outputting circuitry including manually operable means for controlling a time delay between receipt of a flagging signal and output of a corresponding second logic signal;

second logic circuitry connected to the first logic circuitry, the aperture adjust circuitry and the outputting circuitry;

the second logic circuitry sending a pulse to the circuit at concurrence of one of the aperture signals, one of the second logic signals and one of the first logic signals.

6. The hardware of claim 5 wherein the second logic circuitry is comprised of:

a first AND gate receiving the aperture signals from the aperture adjust circuitry;

a second AND gate receiving the second logic signals from the outputting circuitry and receiving first logic signals from the first logic circuitry;

a first flip-flop connected to the AND gates and receiving AND gate signals from the AND gates.

7. The hardware of claim 6 wherein the latch means is a shift register controlling a series of latches.

8. The hardware of claim 7 wherein the first flip flop is connected to and sends a control signal to the shift register and a one shot circuit, the one shot circuit having means to clear the first flip-flop so that the control signal is truncated to become a control pulse.

9. The hardware of claim 8 wherein the shift register is comprised of:

a series of cascaded flip-flops, each of the cascaded flip-flops being connected to one of the latches;

a first connection accepting reset signals from the host computer and sending the reset signals simultaneously to each of the cascaded flip-flops;

a second connection accepting control pulses from the second logic circuitry and sending the control pulses simultaneously to each of the cascaded flip-flops.

10. The hardware of claim 9 wherein the counting circuitry includes:

a synch strip circuit separating the video signal into pictoral subcomponents and the signal subcomponents;

a signal condition circuit processing the signal subcomponents; and

a counter circuit receiving the pictoral subcomponents and processed signal subcomponents.

11. Hardware connecting components of a video system having a camera whose video signal represents pictoral units grouped in frames, a frame grabber, a computer connected to the frame grabber, and a signal generator connected to the hardware;

the hardware comprising;

counting circuitry counting the pictoral units within the frames;

circuit means for receiving count numbers from the counting circuitry and sending selected count numbers to the frame grabber;

first logic circuitry sending a first logic signal to the circuit when the frame grabber can accept the count numbers;

an aperture adjusting circuit converting feedback signals from the camera to aperture signals;

outputting circuitry outputting a second logic signal sending an output in response to a flagging signal from the signal generator, the outputting circuitry including an adjuster delaying response to the flagging signal;

second logic circuitry connected to the first logic circuitry, the aperture adjusting circuitry and the outputting circuitry;

the second logic circuitry sending a logic output to the circuit means at concurrence of one of the aperture signals, one of the second logic signals and one of the first logic signals.

12. The hardware of claim 11 wherein the adjuster is a manually variable means for controlling the delay in the response by the outputting circuitry to the flagging signal.

13. The hardware of claim 11 wherein the aperture circuitry includes means for controlling width of the aperture signal.

14. The hardware of claim 13 wherein the adjuster is a a manually variable means for controlling the delay in response of the outputting circuitry to the flagging signal.