Method and apparatus for a filament channel pass gate ferroelectric capacitor memory cell

• US 5,136,534 A
• Filed: 07/16/1991
• Issued: 08/04/1992
• Est. Priority Date: 06/30/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Clark, David R., McDavid, James M.
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/731,305
• Time in Patent Office: 385 Days
• Field of Search: 365/145, 365/149, 365/182, 365/174, 365/157, 357/23.4, 357/23.6, 357/51
• US Class Current: 365/149
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A memory cell is disclosed which comprises a filament channel transistor and a ferroelectric capacitor formed on a surface of a semiconductor substrate. The transistor comprises a substantially cylindrical channel filament which is formed substantially perpendicular to the substrate surface between the surface and the capacitor. The capacitor comprises a storage layer which can be formed of a ferroelectric material such that the memory cell is nonvolatile. The storage layer may also comprise a high dielectric material such that the memory cell is operable as a dynamic random access memory cell.

Claims

1. A memory cell formed on a surface of a substrate and coupled to a wordline and a bitline, comprising:

a substrate;

a bitline formed at the surface of said substrate;

a transistor, said transistor having a channel comprising a substantially cylindrical semiconductor filament, said channel formed on said bitline and extending substantially perpendicular to and away from said substrate and bitline, an end of said filament coupled to the bitline, the wordline disposed about said filament such that the wordline is operable to actuate said channel; and

a capacitor comprising a first electrode, a second electrode and a storage layer, said first electrode formed substantially vertically above and coupled to an opposite end of said filament such that said filament is between said bitline and said first electrode, said storage layer formed substantially vertically above said first electrode and second electrode formed substantially vertically above said storage layer, said second electrode coupled to a predetermined voltage level.

2. The memory cell of claim 1, wherein said storage layer comprises a dielectric material such that said capacitor is operable as a substantially linear capacitor and the memory cell is operable as a dynamic random access memory cell.

3. The memory cell of claim 1, wherein said storage layer comprises a ferroelectric material such that said capacitor is operable as a nonlinear hysteretic capacitor and the memory cell is operable as a nonvolatile memory cell.

4. The memory cell of claim 1 and further comprising an insulative layer disposed between the wordline and said filament.

5. The memory cell of claim 4, wherein said insulative layer comprises oxide.

6. The memory cell of claim 1 wherein said bitline is formed in the surface of said substrate.

7. The memory cell of claim 1 wherein said bitline comprises a conductive material on an upper surface of said substrate.

8. A memory cell formed on a surface of a substrate of a first conductivity type, comprising:

a substrate;

a conductive bitline formed in the substrate to be of a second conductivity type;

a substantially cylindrical channel filament formed substantially perpendicular to and extending away from and fully above the surface and having a first end coupled to said bitline;

a conductive wordline insulatively disposed about said filament;

a first electrode formed substantially vertically above and coupled to the second end of said filament;

a storage layer formed substantially vertically above and adjoining said first electrode; and

a second electrode formed substantially vertically above and adjoining said capacitor storage body and coupled to a predetermined voltage level.

9. The memory cell of claim 8, wherein said wordline comprises polycrystalline silicon.

10. The memory cell of claim 8 and further comprising an insulative layer disposed about said filament between said filament and said wordline.

11. The memory cell of claim 10, wherein said insulative layer comprises oxide.

12. The memory cell of claim 8, wherein said first and second electrodes comprise nichrome.

13. The memory cell of claim 8 wherein said storage layer comprises a dielectric material.

14. The memory cell of claim 8 wherein said storage layer comprises a ferroelectric material.