Architecture for a signal processing apparatus

• US 5,136,693 A
• Filed: 05/17/1990
• Issued: 08/04/1992
• Est. Priority Date: 06/07/1989
• Status: Expired due to Fees

• Current Assignee: Marconi Holdings Company Limited
• Original Assignee: Marconi Holdings Company Limited
• Inventors: Rice, Colin F.
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US07/524,390
• Time in Patent Office: 810 Days
• Field of Search: 364/200, 364/900, 395/275
• US Class Current: 710/100
• CPC Class Codes: G05B 15/02 electric
• CPC Class Codes: G05B 9/03 with multiple-channel loop, i.e. redundant control systems
• CPC Class Codes: G05D 1/0077 using redundant signals or controls

Abstract

A data processing apparatus for controlling an equipment by operating control devices (1, 3) of the equipment in dependence on signals produced by sensors (5, 7) wherein the sensor signals are processed in three stages. In the first stage the signals are processed in a processor (11) of high operational speed, i.e. number crunching capabilities, and low decision capability. In the second stage processors (19) of lower operational speed and higher decision capability are used. In the third stage processors (27) of still lower speed but higher decision capability are used. This architecture allows the apparatus to be easily reconfigured for use in a wide variety of different applications.

Claims

1. A signal processing apparatus for controlling control devices in dependence on signals derived from sensors, said signal processing apparatus comprising:

(a) at least one first data processor for processing data carried by said signals, in addition to performing routine processing functions;

(b) a plurality of second data processors for processing data produced by said first data processor, in addition to performing routine processing functions;

(c) a plurality of third data processors for processing data produced by said second data processors, in addition to performing routine processing functions;

(d) said first data processor having a higher operational speed than each of said second data processors, and each of said second data processors having a higher operational speed than each of said third data processors;

(e) said first data processor having a lower logical decision capability than each of said second data processors, and each of said second data processors having a lower logical decision capability than each of said third data processors; and

(f) a first data bus, said first data processor, each of said second data processors, and each of said third data processors being individually connected to said first data bus for transfer of data from said first data processor to said second data processors and from said second data processors to said third data processors.

2. A signal processing apparatus according to claim 1, including a further said third data processor acting as a controller for said apparatus.

3. A signal processing apparatus according to claim 1, including a second data bus, said first data processor and each of said second data processors being individually connected to said second data bus for transfer of data from said first data processor to said second data processors.

4. A signal processing apparatus according to claim 1, further including, for each said second data processor, a respective support device connected between said second data processor and said first data bus for reducing said routine processing functions performed by said second data processor.

5. A signal processing apparatus according to claim 1, further including, for each said third data processor, a respective support device connected between said third data processor and said first data bus for reducing said routine processing functions performed by said third data processor.

6. A signal processing apparatus according to claim 1, further including a support device connected between said first data processor and said first data bus for reducing said routine processing functions performed by said first data processor.

7. A signal processing apparatus according to claim 1, further including a global memory connected to said first data bus for use by said first data processor, said plurality of second data processors and said plurality of third data processors.

8. A signal processing apparatus according to claim 1, further including a support device connected to said first data bus for adapting said data output signals of said third data processors to a form suitable for use by said control devices.