Semiconductor device which includes multiple isolated semiconductor segments on one chip

• US 5,138,422 A
• Filed: 11/06/1991
• Issued: 08/11/1992
• Est. Priority Date: 10/27/1987
• Status: Expired due to Term

• Current Assignee: Nippondenso Co., Ltd. (DENSO Corporation)
• Original Assignee: Nippondenso Co., Ltd. (DENSO Corporation)
• Inventors: Tsuzuki, Yukio, Fujii, Tetsuo, Kuroyanagi, Susumu
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Monin, D.
• Application Number:
  US07/790,025
• Time in Patent Office: 279 Days
• Field of Search: 357/30, 357/47, 357/48, 357/49
• US Class Current: 257/401
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76248 using lateral overgrowth techniques, i.e. ELO techniques
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76272 Vertical isolation by lateral overgrowth techniques, i.e. ELO techniques
• CPC Class Codes: H01L 21/76275 Vertical isolation by bonding techniques
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

Disclosed is a semiconductor device which comprises a substrate, an insulating film formed at a predetermined region in the substrate or on the main surface of the substrate, a polycrystalline semiconductor layer formed on at least the insulating film, a single crystal semiconductor layer formed on at least the polycrystalline semiconductor layer, an isolation region formed to extend from the top main surface of the single crystal semiconductor layer to at least the surface of the insulating film, through the polycrystalline semiconductor layer, to electrically isolate a portion formed in the single crystal semiconductor layer surrounded by the isolation region from another portion formed in the single crystal semiconductor layer and not surrounded by the isolation region, at least a semiconductor device formed within the portion surrounded by the isolation region. This semiconductor device has an additional characteristic in that another semiconductor device using another main surface of the substrate as the electrode is provided on the surface of the substrate and the single crystal semiconductor layer, and the plolycrystalline semiconductor layer serves to terminate the electric line of force emitted from the substrate, and therefore, the single crystal semiconductor layer mounted on the polycrystalline semiconductor layer is not affected by the electric line of force. Consequently, a semiconductor device which can operate effectively without being influenced by variations of the electric potential in the substrate can be obtained, and further, an intelligent type power device can be formed in which the power semiconductor device and the semiconductor device controlling the power device are formed in the same substrate but are completely isolated from each other.

Claims

1. A semiconductor device which comprises:

a semiconductor substrate made of a single crystal semiconductor substance;

an insulating film formed locally at a predetermined region on a main surface of the substrate;

a polycrystalline semiconductor layer formed on said insulating film;

a single crystal semiconductor layer formed on said substrate and on said polycrystalline semiconductor layer;

at least one isolation region formed to extend from a top main surface of said single crystal semiconductor layer to at least a surface of said insulating film, through said polycrystalline semiconductor layer and formed substantially vertical to a surface of the substrate, so as to electrically isolate at least a first portion formed in said single crystal semiconductor layer which is provided on said insulating film and surrounded by said isolation region, from a second portion formed in said single crystal semiconductor layer which is provided on said substrate, and not surrounded by said isolation region;

at least a first semiconductor device formed on a main surface of or inside said first portion, for controlling a device formed in a main surface of or inside said second portion; and

at least a second semiconductor device formed on said main surface of or inside said single crystal semiconductor layer forming said second portion on said substrate and not provided with said insulating film thereon, and using another main surface of the substrate opposite to said main surface having said insulating film thereon as a drain electrode to form a power semiconductor device using said second semiconductor device which is controlled by said first semiconductor device, wherein said single crystal semiconductor layer formed on a surface of said substrate in said second portion comprises at least two different unit layers having different amounts of impurities therein, respectively, one of said unit layers adjacent to said substrate has a surface in a same plane as a surface of said polycrystalline semiconductor layer that is formed on the surface of said insulating film.

2. A semiconductor device according to claim 1, wherein said isolation region consists of a groove extended from a top surface of said single crystal semiconductor layer to at least a surface of said insulating film, a wall portion thereof being made of the insulating film and a portion existing between said wall portion thereof being filled with the polycrystalline semiconductor.

3. A semiconductor device according to claim 1, wherein said first portion is provided with a bottom portion comprising a single cry stal semiconductor layer and a polycrystalline semiconductor layer, while on a main side surface of said first portion, mainly a single crystal semiconductor layer is in contact with said isolation region through an insulating film formed on an inner side surface of said isolation region.