Semiconductor device having a particular structure allowing for voltage stress test application

• US 5,138,427 A
• Filed: 07/02/1990
• Issued: 08/11/1992
• Est. Priority Date: 06/30/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Furuyama, Tohru
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US07/547,036
• Time in Patent Office: 771 Days
• Field of Search: 357/45, 357/68, 357/75, 357/23.6, 307/296.6, 307/455
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Since the power-supply and/or signal-transmission wiring layers connected to the semiconductor chip regions are formed, each individual integrated circuit can be burned in on the semiconductor wafer and, in other words, an integrated circuit can be burned in on a wafer level. The integrated circuit can thus be burned in at the end of a wafer process. An assembled semiconductor device is subjected to a high temperature or a high humidity, for checking the reliability of the assembled device.

Claims

1. A semiconductor device comprising:

a semiconductor wafer having a plurality of IC chip regions;

a plurality of first wiring layers formed on said semiconductor wafer and coupled in common to said IC chip regions;

a plurality of memory circuits, each being provided in one of said IC chip regions and each including at least one word line and at least one bit line; and

a plurality of switching means, each being provided in one of said IC chip regions, for rendering in an ON state a connection between word lines of said memory circuits and said first wiring layers and a connection between bit lines of said memory circuits and said first wiring layers during a voltage stress test.

2. A semiconductor device according to claim 1 and further comprising a plurality of power contact terminals formed on said semiconductor wafer, each of said power contact terminals for receiving a power supply voltage and for applying said power supply voltages to said first wiring layers, and at least one signal contact terminal formed on said semiconductor wafer for receiving a signal from outside of said semiconductor and for applying said signal to said first wiring layers.

3. A semiconductor device according to claim 1, wherein said IC chip regions are divided into a plurality of chips, and each of said chips is finished as an integrated circuit.

4. A semiconductor device according to claim 1, wherein said first wiring layers ar formed by patterning a wiring layer from which second wiring layers used in said chip regions are formed by the patterning.

5. A semiconductor device according to claim 4, wherein said first wiring layers are formed on line regions on said semiconductor wafer which are between each of said IC chip regions.

6. A semiconductor device according to claim 4, wherein said first wiring layers are disconnected from said second wiring layers before said semiconductor wafer is physically separated into said IC chip regions.

7. A semiconductor device according to claim 1, wherein said first wiring layers are formed by patterning a wiring layer different from that from which second wiring layers used in said IC chip regions are formed by patterning.

8. A semiconductor device according to claim 7, wherein said first wiring layers are formed on line regions on said semiconductor wafer which are between each of said IC chip regions.

9. A semiconductor device according to claim 8, wherein said first wiring layers are removed before said semiconductor wafer is physically separated into said IC chip regions.

10. A semiconductor device according to claim 4, wherein a resistor element is interposed between said first wiring layers and second wiring layers used in said IC chip regions.

11. A semiconductor device according to claim 10, wherein said resistor element has a resistance which is higher than a sheet resistance of said first and second wiring layers.

12. A semiconductor device comprising:

a semiconductor wafer having a plurality of IC chip regions;

a plurality of dynamic memory circuits, each being provided in said IC chip regions;

two power supply lines, arranged on said semiconductor wafer and coupled in common to said dynamic memory circuits, for application of a power supply voltage and a ground potential; and

two signal lines, arranged on said semiconductor wafer and coupled in common to said dynamic memory circuits, for supply of a RAS (row address strobe) signal and a CAS (column address strobe) signal.

13. A semiconductor device according to claim 12, further comprising a plurality of power contact terminals formed on said semiconductor wafer, each of said power contact terminals for receiving either said power supply voltage of said ground potential and for applying said power supply voltage or said ground potential to said two power supply lines, and a plurality of signal contact terminals formed on said semiconductor wafer, each of said signal contact terminals for receiving a signal from outside of said semiconductor wafer and for applying one of said signals to said signal lines.

14. A semiconductor device according to claim 12, wherein said IC chip regions are divided into a plurality of chips, and each of said chips is finished as an integrated circuit.

15. A semiconductor device according to claim 12, wherein said two power supply lines and said two signal lines are formed by patterning a wiring layer from which second wiring layers used in said IC chip regions are formed by the patterning.

16. A semiconductor device according to claim 15, wherein said two power supply lines and said two signal lines are formed on line regions on said semiconductor wafer which ar between each of said IC chip regions.

17. A semiconductor device according to claim 16, wherein said two power supply lines and said two signal lines are disconnected from said second wiring layers before said semiconductor wafer is physically separated into said IC chip regions.

21. A semiconductor device according to claim 12, wherein two resistor elements are interposed, one between said two power supply lines and second wiring lines used in said IC chip regions, and the other between said two signal lines and said second wiring lines.

22. A semiconductor device according to claim 21, wherein each of said resistor elements has a resistance which is higher than a sheet resistance of said second wiring layers.

18. A semiconductor device according to claim 36, wherein said two power supply lines and said two signal lines are formed by patterning a wiring layer different from that from which second wiring layers used in said IC chip regions are formed by patterning.

19. A semiconductor device according to claim 18, wherein said two power supply lines and said two signal lines are formed on line regions on said semiconductor wafer.

20. A semiconductor device according to claim 19, wherein said two power supply lines and said two signal lines are removed before said semiconductor wafer is physically separated into said IC chip regions.