Method and apparatus for erasing an array of electrically erasable EPROM cells

• US 5,138,576 A
• Filed: 11/06/1991
• Issued: 08/11/1992
• Est. Priority Date: 11/06/1991
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Madurawe, Raminda
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/788,606
• Time in Patent Office: 279 Days
• Field of Search: 365/185, 365/218, 365/201, 365/205, 357/23.5
• US Class Current: 365/185.3
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing

Abstract

A method and apparatus for erasing an array of electrically erasable EPROM cells that avoids overerasure and allows programming or erasure of individual cells are provided. An erase line for each column of the array applies erase potential to the erase node of each cell in the column, provided that the erase node is connected to the erase line by a transistor controlled by a row select line. A sense amplifier determines when each cell begins to conduct and disconnects that cell from its erase line. By selecting a particular row, and then applying erase potential only to selected erase lines, a pattern of erased and programmed cells can be created in each row. The pattern differs from row to row depending on which erase lines have erase potential applied when that row is selected. Bias differences between erase and read modes assure that the erased cells, which have gone slightly into depletion, are not in depletion in normal operation.

Claims

1. Apparatus for erasing an array of Flash cells and for stopping erasure of each cell in said array of cells on onset of conduction by said cell, each of said cells having a gate, a source, a drain, a floating gate from which charge must be removed by placing a high potential difference thereacross to erase the cell, and an erase node for applying said high potential across said floating gate, said cells connected in parallel columns, the sources of all cells in each said column being connected in common to a respective source line for said column and the drains of all cells in each said column being connected in common to a respective drain line for said column, said cells also arranged in parallel rows orthogonal to said columns, said gates of said cells in each one of said rows being connected to a respective gate line for said one of said rows, said apparatus comprising:

a supply of ground potential;

means for applying ground potential to each of said source lines;

means for applying ground potential to each of said gates;

a supply of high positive potential;

a plurality of column erase lines, each associated with a respective column, for connecting the erase node of each cell in said respective column to said supply of high positive potential;

a plurality of sense amplifier means, each associated with a respective column for sensing conduction between the drain line and the source line of said respective column;

a plurality of switching means, each associated with a respective column, for switchably connecting each respective column erase line to said supply of high positive potential responsive to output of a respective one of said sense amplifier means, said respective column erase line being connected to said supply of high positive potential in absence of conduction and being disconnected from said supply of high positive potential when there is conduction;

a plurality of selecting means, each associated with one of said cells for selectively connecting the erase node of said one of said cells to said respective column erase line; and

a plurality of select lines, each associated with a respective row for actuating said selecting means of all cells in said respective row;

wherein;

when a row is selected by assertion of its respective select line, said high positive potential causes electrons to flow off said floating gates of each of said cells in said selected row whose respective switching means is switched to connect its respective column erase line to said supply of high positive potential, such that as enough electrons have been removed from said floating gate of each one of said cells in said selected row;

said one of said cells begins to conduct,

said output of said sense amplifier associated with the column of said one of said cells changes, and

said switching means disconnects the respective column erase line associated with said one of said cells from said supply of high positive potential, insufficient potential remaining across said floating gate to remove additional electrons, whereby erasure of each cell in said selected row is stopped at onset of conduction by said cell.

2. The apparatus of claim 1 further comprising means for controllably connecting each respective column erase line to said supply of high positive potential, whereby only desired ones of said cells in said selected row may be erased.

3. The apparatus of claim 1 wherein said erase node comprises a tunnel capacitor.

4. The apparatus of claim 1 wherein said switching means comprises a transistor.

5. The apparatus of claim 4 wherein said transistor is a field effect transistor.

6. The apparatus of claim 1 wherein said selecting means comprises a transistor.

7. The apparatus of claim 6 wherein said transistor is a field effect transistor.

8. The apparatus of claim 1 wherein said Flash cell comprises an EEPROM.

9. The apparatus of claim 1 wherein said Flash cell comprises a Flash EPROM.

10. A method of erasing an array of Flash cells and for stopping erasure of each cell in said array of cells on onset of conduction by said cell, each of said cells having a gate, a source, a drain, a floating gate from which charge must be removed by placing a high potential difference thereacross to erase the cell, and an erase node for applying said high potential across said floating gate, said cells connected in parallel columns, the sources of all cells in each said column being connected in common to a respective source line for said column and the drains of all cells in each said column being connected in common to a respective drain line for said column, said cells also arranged in parallel rows orthogonal to said columns, said gates of said cells in each one of said rows being connected to a respective gate line for said one of said rows, said apparatus comprising:

applying ground potential to each of said source lines;

applying ground potential to each of said gates;

providing a plurality of column erase lines, each associated with a respective column, for connecting the erase node of each cell in said respective column to said supply of high positive potential;

switchably connecting each respective column erase line to said supply of high positive potential responsive to the conduction state of the respective drain and source lines, said respective column erase line being connected to said supply of high positive potential in absence of conduction and being disconnected from said supply of high positive potential when there is conduction;

selectively connecting the erase nodes of cells in a selected row to their respective column erase lines; and

sensing the conduction state of said drain and source lines;

wherein;

when a row and columns are selected, said high positive potential causes electrons to flow off said floating gates of each of said cells in a selected row and a selected column, such that as enough electrons have been removed from said floating gate of each one of said cells in said row;

said one of said cells begins to conduct, and

said conduction is sensed and the respective column erase line is disconnected from said cell, in sufficient potential remaining across said floating gate to remove additional electrons, whereby erasure of each cell in said selected row is stopped at onset of conduction by said cells.

11. The method of claim 10 further comprising controllably connecting each respective column erase line to said supply of high positive potential, whereby only desired ones of said cells in said selected row may be erased.