Sequential logic circuit device

• US 5,140,176 A
• Filed: 03/07/1991
• Issued: 08/18/1992
• Est. Priority Date: 03/09/1990
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Okino, Noboru
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US07/666,001
• Time in Patent Office: 530 Days
• Field of Search: 307/272.1, 307/272.2, 307/272.3, 307/291
• US Class Current: 327/217
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G05B 19/0423 Input/output

Abstract

A logic circuit part, which is composed of a flip-flop group and a combinational circuit and performs a sequential logic operation, is added with a specify circuit for selectively specifying desired flip-flop circuits in the flip-flop group and a write circuit for applying a set or reset signal to the flip-flop circuits selectively specified by the specify circuit. Each flip-flop circuit includes: a flip-flop for writing input data in response to a system clock; a first AND gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the set signal to set the flip-flop; a second AND gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the reset signal to reset the flip-flop; and a third and gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the output logic of the flip-flop to the outside.

Claims

1. A sequential logic circuit device comprising:

a logic circuit part composed of a flip-flop group including a plurality of flip-flop circuits and a combinatorial circuit connected to said flip-flop group, for performing a predetermined sequential logic operation;

specify circuit means for selectively specifying said flip-flop circuits in said flip-flop group in accordance with an external address, said specify circuit means including decoder means for decoding said address and applying a decoded address signal to each said flip-flop circuit selectively specified in said flip-flop group; and

write circuit means whereby set or reset signals are applied to said flip-flop circuits selectively specified by said specify circuit means, in accordance with an external setting signal;

wherein each of said flip-flop circuits in said flip-flop group includes;

flip-flop means for storing logic input data;

first gate means responsive to said decoded address signal to apply said set signal to said flip-flop means to set said flip-flop means;

second gate means responsive to said decoded address signal and cleared by an external clear signal to apply said reset signal to said flip-flop means to reset said flip-flop means; and

third gate means for externally outputting the logic in said flip-flop means in response to said decoded address signal.

2. The sequential logic circuit device of claim 1, wherein said first, second and third gate means are AND gates.

3. The sequential logic circuit device of claim 2, wherein said flip-flop means of said each flip-flop circuit is a D type flip-flop which stores said input data in response to an external system clock.