Low di/dt BiCMOS output buffer with improved speed

• US 5,140,191 A
• Filed: 11/05/1990
• Issued: 08/18/1992
• Est. Priority Date: 11/05/1990
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Molorola Incorporated
• Inventors: Pelley, Perry H. III, Nogle, Scott G.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US07/610,172
• Time in Patent Office: 652 Days
• Field of Search: 307/475, 307/296.8, 307/443, 307/296.6, 307/270, 307/263, 307/264, 307/246, 307/446
• US Class Current: 326/87
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents

Abstract

An output buffer for a device such as a memory comprises a voltage regulator, a current source portion, a switching portion, and an output portion. The voltage regulator provides a constant voltage independent of fluctuations between first and second power supply voltages. The current source portion provides first and second currents to first and second nodes to limit the rate at which transistors in the output portion become conductive. The switching portion provides voltage signals on the first and second nodes respectively in response to positive and negative voltage differences between first and second input voltages. The output portion provides an output signal at either a logic high or a logic low voltage respectively in resonse to the voltage signals at the first and second nodes. The current source portion allows the use of faster bipolar transistors to improve the speed of the output buffer while maintaining accepable di/dt.

Claims

1. An output buffer comprising:

a voltage regulator, coupled to first and second power supply voltage terminals, for providing a regulated voltage characterized as having a constant voltage substantially independent of fluctuations in voltage between said first power supply voltage terminal and said second power supply voltage terminal;

first and second current sources, each coupled to said voltage regulator, for providing first and second currents from said voltage regulator, respectively, to first and second nodes;

switching means, coupled to said first and second current sources, for providing voltage signals at said first and second nodes respectively in response to positive and negative voltage differences between first and second input voltages;

a third current source, having a first terminal coupled to said switching means, and a second terminal coupled to said second power supply voltage terminal;

output means, coupled to said first and second nodes, for providing an output signal at a logic high voltage in response to said voltage signal at said first node, and for providing said output signal as a logic low voltage in response to said voltage signal at said second node.

2. The output buffer of claim 1 wherein said switching means comprises:

a first transistor, having a first current electrode coupled to said first node, a control electrode for receiving said second input voltage, and a second current electrode coupled to said third current source; and

a second transistor having a first current electrode coupled to said second node, a control electrode for receiving said first input voltage, and a second current electrode coupled to said second current electrode of said first transistor.

3. The output buffer of claim 2 wherein said first and second transistors are bipolar transistors.

4. The output buffer of claim 2 wherein a current provided by said current source exceeds a sum of both said first current and said second current.

5. The output buffer of claim 1 wherein said output means comprises:

clamping means, coupled to said first and second nodes, for maintaining a predetermined minimum voltage on said first and second nodes;

pullup means for providing a first signal in response to said voltage at said first node, a logic high voltage of said first signal exceeding a logic high voltage of said voltage at said first node by a predetermined voltage; and

an output stage for providing said output signal at either a logic high voltage in response to either said first signal or to said voltage at said first node, or a logic low voltage in response to said voltage at said second node.

6. The output buffer of claim 1 wherein said output means comprises:

clamping means, coupled to said first and second nodes, for maintaining a predetermined minimum voltage on said first and second nodes;

level shift means, coupled to said first and second nodes, for providing a first signal at said voltage of said first node minus a first predetermined voltage, and for providing a second signal at said voltage of said second node minus a second predetermined voltage;

pullup means for providing a third signal in response to said first signal, a logic high voltage of said third signal exceeding a logic high voltage of said first signal by a third predetermined voltage; and

an output stage, coupled to said level shifter, for providing said output signal at either a logic high voltage in response to said first and third signals, or a logic low voltage in response to said second signal.

7. The output buffer of claim 6 wherein said output stage comprises:

a first transistor having a collector coupled to said first power supply voltage terminal, a base for receiving said first signal, and an emitter for providing said output signal;

a second transistor having a collector coupled to said first power supply voltage terminal, a base for receiving said third signal, and an emitter;

a resistor having a first terminal coupled to said emitter of said second transistor, and a second terminal coupled to said emitter of said first transistor; and

a third transistor having a first current electrode coupled to said emitter of said first transistor, a control electrode for receiving said second signal, and a second current electrode coupled to said second power supply voltage terminal.

8. The output buffer of claim 7 further comprising a fourth transistor having both a collector and a base coupled to said base of said first transistor, and having an emitter coupled to said emitter of said first transistor.

9. The output buffer of claim 6 further comprising feedback means coupled to said level shifter and to said output stage, for maintaining said first and third signals at substantially a second predetermined minimum voltage in response to a select signal.

10. The output buffer of claim 9 wherein said feedback means comprises:

a first resistor having a first terminal coupled to said first power supply voltage terminal, and a second terminal;

a transistor having a first current electrode coupled to said second terminal of said first resistor, a control electrode for receiving said output signal, and a second current electrode for providing said first signal; and

a second resistor having a first terminal coupled to said second current electrode of said transistor, and a second terminal coupled to said second power supply voltage terminal.

11. An output buffer coupled to first and second power supply voltage terminals comprising:

input means for either, providing first and second signals in response to a voltage difference between true and complementary input voltages, or for providing said first and second signals at the second power supply voltage in response to a select signal;

clamp means, coupled to said input means, for clamping said first and second signals at a first predetermined minimum voltage;

a level shifter, coupled to said input means, for providing third and fourth signals respectively at voltages of said first and second signals minus a predetermined voltage;

feedback means, coupled to said level shifter, for maintaining said first and third signals at a second predetermined minimum voltage in response to said select signal;

pullup means for providing a fifth output signal in response to said third signal; and

output stage means for providing a data output signal at a data output node, said output stage means providing said data output signal at a logic high voltage in response to at least one of said third signal and said fifth signal, and for providing said data output signal at a logic low voltage in response to said fourth signal.

12. The output buffer of claim 11 wherein said output means comprises:

a first transistor having a collector coupled to the first power supply voltage terminal, a base for receiving said third signal, and an emitter for providing said data output signal;

a second transistor having a collector coupled to the first power supply voltage terminal, a base for receiving said fifth output signal, and an emitter;

a resistor having a first terminal coupled to said emitter of said second transistor, and a second terminal coupled to said emitter of said first transistor; and

a third transistor having a first current electrode coupled to said emitter of said first transistor, a control electrode for receiving said fourth signal, and a second current electrode coupled to the second power supply voltage terminal.

13. The output buffer of claim 12 wherein said output means further comprises a fourth transistor having both a collector and a base coupled to said base of said first transistor, and an emitter coupled to said emitter of said first transistor.

14. The output buffer of claim 11 wherein said input means comprises:

a first transistor having a first current electrode coupled to a reference voltage terminal, a control electrode for receiving a first bias voltage, and a second current electrodes;

a second transistor having a first current electrode coupled to said reference voltage terminal, a control electrode for receiving a second bias signal, and a second current electrode;

a third transistor having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving said select signal, and a second current electrode for providing said second signal;

a fourth transistor having a first current electrode coupled to said second current electrode of said second transistor, a control electrode for receiving said select signal, and a second current electrode for providing said first signal;

a fifth transistor having a first current electrode coupled to said second current electrode of said third transistor, a control electrode for receiving said true input voltage, and a second current electrode;

a sixth transistor having a first current electrode coupled to said second current electrode of said fourth transistor, a control electrode for receiving said complementary input signal, and a second current electrode coupled to said second current electrode of said fifth transistor; and

a current source coupled to said second current electrodes of said fifth and sixth transistors, for providing a predetermined current from said second current electrodes of said fifth and sixth transistors to the second power supply voltage terminal.

15. The output buffer of claim 14 wherein said fifth and sixth transistors are each bipolar transistors.

16. The output buffer of claim 11 wherein said level shifter comprises:

a first transistor having a collector coupled to the first power supply voltage terminal, a base for receiving said first signal, and an emitter for providing said third signal;

first bias means coupled to said emitter of said first transistor, for providing a first predetermined current from said emitter of said first transistor to the second power supply voltage terminal when a second select signal is active;

a second transistor having a collector coupled to the first power supply voltage terminal, a base for receiving said second signal, and an emitter for providing said second output signal; and

second bias means coupled to said emitter of said second transistor, for providing a second predetermined current to said emitter of said second transistor to the second power supply voltage terminal.

17. The output buffer of claim 11 wherein said feedback means comprises:

a first resistor having a first terminal coupled to said second power supply voltage terminal, and a second terminal;

a transistor having a first current electrode coupled to said second terminal of said resistor, a control electrode for receiving said data output signal, and a second current electrode for providing said third signal; and

a second resistor having a first terminal coupled to said second current electrode of said transistor, and a second terminal coupled to said first power supply voltage terminal.

18. The output buffer of claim 17 wherein said feedback means further comprises:

a second transistor having a first current electrode for receiving said fourth signal, a control electrode for receiving said third signal, and a second current electrode; and

a third resistor having a first terminal coupled to said second current electrode of said second transistor, and a second terminal coupled to said first power supply voltage terminal.

19. The output buffer of claim 11 wherein said pullup means comprises:

a first transistor having a first current electrode for receiving said reference voltage, a control electrode for receiving said third signal, and a second current electrode;

a second transistor having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving said third signal, and a second current electrode;

a third transistor having a first current electrode coupled to said second current electrode of said second transistor, a control electrode for receiving a second select signal, and a second current electrode coupled to said first power supply voltage terminal;

a fourth transistor having a first current electrode for receiving said reference voltage, a control electrode for receiving said select signal, and a second current electrode coupled to said second current electrode of said first transistor;

a fifth transistor having a first current electrode for receiving a second reference voltage, a control electrode coupled to said second current electrode of said first transistor, and a second current electrode for providing said fifth signal;

a sixth transistor having a first current electrode for receiving said third signal, a control electrode for receiving said reference voltage, and a second current electrode coupled to said second current electrode of said fifth transistor; and

a seventh transistor having a first current electrode for receiving said third signal, a control electrode for receiving said second select signal, and a second current electrode coupled to said second current electrode of said fifth transistor.

20. An output buffer comprising:

input means for providing first and second signals respectively in response to positive and negative voltage differences between true and complementary input voltages, a logic high voltage of said first and second signals equal to a first predetermined voltage;

pullup means for providing a third signal in response to said first signal, a logic high voltage of said third signal equal to a second predetermined voltage;

a first transistor having a collector coupled to a first power supply voltage terminal, a base for receiving said first signal, and an emitter for providing a data output signal of the output buffer;

a second transistor having a collector coupled to said first power supply voltage terminal, a base for receiving said third signal, and an emitter;

a resistor having a first terminal coupled to said emitter of said second transistor, amd a second terminal coupled to said emitter of said first transistor; and

a third transistor having a first current electrode coupled to said emitter of said first transistor, a control electrode for receiving said second signal, and a second current electrode coupled to a second power supply voltage terminal.

21. The output buffer of claim 20 further comprising a fourth transistor having both a base and a collector coupled to said base of said first transistor, and an emitter coupled to said emitter of said first transistor.

22. The output buffer of claim 21 further comprising:

a second resistor having a first terminal coupled to said first power supply voltage terminal, and a second terminal;

a fifth transistor having a first current electrode coupled to said second terminal of said second resistor, a control electrode for receiving said data output signal, and a second current electrode for providing said first signal; and

a third resistor having a first terminal coupled to said second current electrode of said fifth transistor, and a second terminal coupled to said second power supply voltage terminal.