Converter comparator cell with improved resolution

• US 5,140,326 A
• Filed: 01/29/1991
• Issued: 08/18/1992
• Est. Priority Date: 01/29/1991
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Tu, Shen, Fisher, Gregory J., Bacrania, Kantilal
• Primary Examiner(s): Logan, Sharon D.
• Application Number:
  US07/647,346
• Time in Patent Office: 567 Days
• Field of Search: 341/159, 341/158, 341/155, 307/355, 307/356, 307/530, 307/362
• US Class Current: 341/159
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors
• CPC Class Codes: H03K 5/249 using clock signals
• CPC Class Codes: H03M 1/365 the voltage divider being a single resistor string

Abstract

A comparator having a differential sense amplifier connected to the output of an input comparator, and the decoding logic connected between the sense amplifier and the output latch. The comparator is designed for a flash A/D converter having a reference signal generator for one or more of the sense amplifiers.

Claims

1. A comparator comprising:

comparator means, having first and second signal inputs and an output, for comparing signals at said first and second inputs and providing a signal at said output of said comparator means as function of said comparison;

sense amplifier means including a differential sense amplifier, having a first input connected to said output of said comparator means and a second input connected to a reference signal and an output, for sensing signals at said first input and providing an amplified signal at said output of said sense amplifier; and

output means, having an input connected to said output of said sense amplifier and an output, for receiving and latching said amplified signal.

2. A comparator according to claim 1, wherein said comparator means includes a two stage autozero comparator.

3. A comparator according to claim 1, including a reference signal generator connected to said second input of said differential sense amplifier and said reference signal generator having an output stage matched to the output stage of said comparator means.

4. A comparator according to claim 1, wherein said sense amplifier means includes matched input buffers at said first and second inputs of said differential sense amplifier.

6. A comparator according to claim 1, wherein said sense amplifier means includes first and second sense transistors connected respectively to said first and second inputs of said differential sense amplifier, and first and second cross-coupled regenerative active loads connected to said first and second sense transistors respectively.

7. A comparator according to claim 1, wherein said sense amplifier means includes output buffer means connecting said output of said differential sense amplifier to said input of said output means.

5. A comparator according to claim 5 wherein said input buffers include:

two series connected transistors at said first input, one of which has a control electrode connected to said comparator means and another of which has a control electrode connected to said reference signal; and

two series connected transistors at said second input each having a control electrode connected to said reference signal.

8. A comparator comprising:

comparator means, having first and second signal inputs and an output, for comparing signals at said first and second inputs and providing a signal at said output of said comparator means as function of said comparison;

sense amplifier means, having an input connected to said output of said comparator means and an output, for sensing signals at said input of said sense amplifier means and providing an amplified signal at said output of said sense amplifier means;

decoding means, having an input connected to said output of said sense amplifier means and an output, for decoding said amplified signal into data; and

latch means, having an input connected to said output of said decoding means and an output, for receiving data from said decoding means and latching said received data.

9. A comparator according to claim 8, wherein said latch includes a D-type master-slave flip-flop.

10. A comparator according to claim 8, including clock means for generating a clock signal to control said comparator means;

and strobe means for generating a strobe signal which leads said clock signal with respect to phase and controls said sense amplifier means and said latch means.

11. A comparator comprising:

comparator means having first and second signal inputs and an output for comparing signals at said first and second inputs and providing a signal at said output of said comparator means as function of said comparison;

decoding means, having an input connected to said output of said comparator means and an output, for decoding said amplified signal into data; and

latch means, having an input connected to said output of said decoding means and an output, for receiving data from said decoding means and latching said received data.

12. A comparator according to claim 11, wherein said comparator means includes a two stage autozero comparator.

13. A comparator according to claim 11, wherein said latch means includes master-slave flip-flop.

14. A comparator according to claim 13, wherein said master-slave flip-flop is a pair of D-type latches.

15. A comparator according to claim 11, including clock means for generating a clock signal to control said comparator means;

and

strobe means for generating a strobe signal which leads said clock signal with respect to phase and controls said latch means.

16. An analog-to-digital converter comprising:

input means for receiving an analog signal;

a plurality of parallel comparator means, each having a first input connected to said input means and a second input connected to a respective reference value, for providing a signal at said output of said comparator means as function of said comparison;

a plurality of sense amplifier means each including a differential sense amplifier, having a first input connected to said output of a respective comparator means and a second input connected to a reference signal and an output, for sensing signals at said first input of said differential sense amplifier and providing an amplified signal at said output of said sense amplifier; and

output means, having an input connected to said output of said plurality of sense amplifiers and an output, for receiving and decoding said amplified signal into a digital signal.

17. An analog-to-digital converter according to claim 16, wherein said comparator means each include a two stage autozero comparator.

18. An analog-to-digital converter according to claim 16, including one or more reference signal generators connected to said second input of a respective differential sense amplifier and each reference signal generator having an output stage matched to the output stage of said comparator means.

19. An analog-to-digital converter according to claim 16, wherein said each reference signal generator is connected to said second input of a respective group of differential sense amplifiers.

20. An analog-to-digital converter according to claim 16, wherein said sense amplifier means each includes matched input buffers at said first and second inputs of said differential sense amplifier.

21. An analog-to-digital converter according to claim 23 wherein said input buffers include:

two series connected transistors at said first input, one of which has a control electrode connected to said comparator means and another of which has a control electrode connected to said reference signal generator; and

two series connected transistors at said second input each having a control electrode connected to said reference signal generator.

22. An analog-to-digital converter according to claim 16, wherein said sense amplifier means each include first and second sense transistors connected respectively to said first and second inputs of said differential sense amplifier, and first and second cross-coupled regenerative active loads connected to said first and second sense transistors respectively.

23. An analog-to-digital converter according to claim 16, wherein said sense amplifier means each include output buffer means connecting said output of said differential sense amplifier to said input of said output means.

24. An analog-to-digital converter comprising:

input means for receiving an analog signal;

a plurality of parallel comparator means, each having a first input connected to said input means and a second input connected to a respective reference value, for providing a signal at said output of said comparator means as function of said comparison;

a plurality of sense amplifier means, having an input connected to said output of a respective comparator means and an output, for sensing signals at said input of said sense amplifier means and providing an amplified signal at said output of said sense amplifier means;

a plurality of decoding means, having an input connected to said output of a respective sense amplifier means and an output, for decoding said amplified signal into data; and

a plurality of latch means, having an input connected to said output of a respective decoding means and an output, for receiving data from said decoding means and latching said received data.

25. An analog-to-digital converter according to claim 24, wherein each of said latch means includes a D-type master-slave flip-flop.

26. An analog-to-digital converter according to claim 24, including clock means for generating a clock signal to control said comparator means;

and strobe means for generating a strobe signal which leads said clock signal with respect to phase and controls said sense amplifier means and said latch means.

27. A comparator comprising:

comparator means, having first and second signal inputs and an output, for comparing signals at said first and second inputs and providing a signal at said output of said comparator means as function of said comparison;

sense amplifier means, having an input connected to said output of said comparator means and an output, for sensing signals at said input of said sense amplifier means and providing an amplified signal at said output of said sense amplifier means;

output means, having an input connected to said output of said sense amplifier means and an output, for receiving and latching said amplified signal;

clock means for generating a clock signal to control said comparator means; and

strobe means for generating a strobe signal which leads said clock signal with respect to phase and controls said second amplifier means.

28. An analog-to-digital converter comprising:

input means for receiving an analog signal;

a plurality of parallel comparator means, each having a first input connected to said input means and a second input connected to a respective reference value, for providing a signal at said output of said comparator means as function of said comparison;

a plurality of sense amplifier means, having an input connected to said output of a respective comparator means and an output, for sensing signals at said input of said sense amplifier means and providing an amplified signal at said output of said sense amplifier means;

output means, having an input connected to said output of said plurality of sense amplifier means and an output, for receiving and decoding said amplified signal into a digital signal;

clock means for generating a clock signal to control said comparator means; and

strobe means for generating a strobe signal which leads said clock signal with respect to phase and controls said sense amplifier means.