Semiconductor assembly utilizing elastomeric single axis conductive interconnect

• US 5,140,405 A
• Filed: 03/29/1991
• Issued: 08/18/1992
• Est. Priority Date: 08/30/1990
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Brooks, Jerry M., Farnworth, Warren M., King, Jerrold L., McGill, George P.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/677,439
• Time in Patent Office: 508 Days
• Field of Search: 357/72, 357/74, 357/79, 357/75, 357/68, 357/67, 439/91, 361/400
• US Class Current: 257/727
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32227 the layer connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83851 being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An semiconductor assembly includes at least one die having substantially planar first and second engagement surfaces and external edges which define a die shape. A base having an opening formed therein receives the die. The base opening has peripheral edges which define an opening shape and size which is complementary to the die external shape. The opening edges engage the die edges to spatially fix the die in a selected orientation in a plane parallel to the die first planar engagement surface. An interconnecting plate has at least one substantially planar engagement surface facing the first planar engagement surface of the die received within the base opening. At least one conductive pad on the plate planar engagement surface is spatially aligned or registered with a corresponding conductive pad on the first engagement surface of the die. A sheet of anisotropically conductive elastomeric material is interposed between the base and interconnecting plate between the first engagement surface of the die and engagement surface of the interconnecting plate. The base and interconnecting plate are clamped relative to one another in selected registration, sandwiching the anisotropically conductive elastomeric material therebetween. This conductively engages the at least one conductive pad of the die with the at least one conductive pad of the interconnecting plate through the sheet of anisotropically conductive elastomeric material.

Claims

1. A semiconductor assembly comprising:

a die having substantially planar first and second engagement surfaces, a defined thickness therebetween, and having external edges which define a die external shape, the first engagement surface including one or more conductive pads;

a base having an opening formed therein, the base opening having peripheral edges which define an opening shape which is complementary to the die external shape, the opening being sized to receive and engage the die, the die being so received within the base opening with the opening edges engaging the die edges to spatially fix the die in a selected orientation in a plane parallel to the die first planar engagement surface;

an interconnecting plate having at least one substantially planar engagement surface facing the first planar engagement surface of the die received within the base opening, the plate planar engagement surface having one or more conductive pads and conductive traces formed thereon, at least one conductive pad of the plate planar engagement surface being spatially aligned with one conductive pad on the first engagement surface of the die received within the base opening;

a sheet of anisotropically conductive elastomeric material that is electrically conductive in a direction across its thickness, the sheet being interposed between the base and interconnecting plate between the first engagement surface of the die and engagement surface of the interconnecting plate; and

clamping means engaging the base and interconnecting plate for urging the die and plate toward one another in spatial registration to conductively engage the at least one conductive pad of the die with the at least one conductive pad of the interconnecting plate through the sheet of anisotropically conductive elastomeric material.

2. The semiconductor assembly of claim 1 wherein the interconnecting plate further includes a plurality of edge conductors operably connected to the traces.

3. The semiconductor assembly of claim 1 wherein the interconnecting plate includes a second planar engagement surface opposing the one planar engagement surface, the base includes a planar engagement surface, the assembly further comprising rigid backing plates overlying the second planar engagement surface of the interconnecting plate and the planar engagement surface of the base.

4. The semiconductor assembly of claim 1 wherein the base includes first and second engagement surfaces and a thickness defined therebetween, the base opening extending entirely through the base between the base first and second engagement surfaces.

5. The semiconductor assembly of claim 4 wherein the interconnecting plate includes a second planar engagement surface opposing the one planar engagement surface, the assembly further comprising rigid backing plates overlying the second planar engagement surface of the interconnecting plate and the second planar engagement surface of the base.

6. The semiconductor assembly of claim 1 wherein the base includes a first planar engagement surface, the base opening being defined by a recess formed into the base from the first base planar engagement surface, the recess having a planar recess base surface, the recess having a depth which is substantially equal to the die thickness, the die being received within the recess with the die second planar engagement surface being received against the planar recess base surface and the die first planar engagement surface being substantially coplanar with the first base planar engagement surface.

7. The semiconductor assembly of claim 6 wherein the interconnecting plate includes a second planar engagement surface opposing the one planar engagement surface, the base includes a second planar engagement surface, the assembly further comprising rigid backing plates overlying the second planar engagement surface of the interconnecting plate and the second planar engagement surface of the base.

8. A semiconductor assembly comprising:

a plurality of dies having substantially planar first and second engagement surfaces, engagement surfaces including one or more conductive pads, defined thicknesses therebetween, and external edges which define die eternal shapes, the first engagement surfaces including one or more conductive pads;

a base having a plurality of openings formed therein, the base openings having peripheral edges which define opening shapes which are complementary to the respective die external shapes, the respective openings being sized to receive and engage respective dies, the respective dies being so received within the respective base openings with the opening edges engaging the respective die edges to spatially fix the respective dies in a selected orientation in a plane parallel to the respective die first planar engagement surfaces;

an interconnecting plate having at least one substantially planar engagement surface facing the first planar engagement surfaces of the dies received within the base openings, the plate planar engagement having a plurality of conductive pads and traces formed thereon, the conductive pads of the plate planar engagement surface being spatially aligned with respective conductive pads on the first planar engagement surfaces of the dies received within the base openings;

a sheet of anisotropically conductive elastomeric material that is electrically conductive in a direction across its thickness, the sheet being interposed between the base and interconnecting plate between the first engagement surfaces of the dies and engagement surface of the interconnecting plate; and

clamping means engaging the base and interconnecting plate for urging the dies and plate toward one another in spatial registration to conductively engage the conductive pads of the dies with conductive pads of the interconnecting plate through the sheet of anisotropically conductive elastomeric material.

9. The semiconductor assembly of claim 8 wherein the interconnecting plate further includes a plurality of edge conductors operably connected to the traces.

10. The semiconductor assembly of claim 8 wherein the interconnecting plate includes a second planar engagement surface opposing the one planar engagement surface, the base includes a planar engagement surface, the assembly further comprising rigid backing plates overlying the second planar engagement surface of the interconnecting plate and the planar engagement surface of the base.

11. The semiconductor assembly of claim 8 wherein the base includes first and second engagement surfaces and a thickness defined therebetween, the base openings extending entirely through the base between the first and second engagement surfaces.

12. The semiconductor assembly of claim 11 wherein the interconnecting plate includes a second planar engagement surface opposing the one planar engagement surface, the assembly further comprising rigid backing plates overlying the second planar engagement surface of the interconnecting plate and the second planar engagement surface of the base.

13. The semiconductor assembly of claim 8 wherein the base includes a first planar engagement surface, the base openings being defined by recesses formed into the base from the first base planar engagement surface, the recesses having planar recess base surfaces, the recesses having depths which are substantially equal to the respective die thickness, the respective dies being received within the respective recessed with the die second planar engagement surfaces being received against the planar recess base surfaces and the die first planar engagement surfaces being substantially coplanar with the first base planar engagement surface.

14. The semiconductor assembly of claim 13 wherein the interconnecting plate includes a second planar engagement surface opposing the one planar engagement surface, the base includes a second planar engagement surface, the assembly further comprising rigid backing plates overlying the second planar engagement surface of the interconnecting plate and the second planar engagement surface of the base.

15. The semiconductor assembly of claim 13 wherein the dies comprise electronic memories arranged in a single in-line memory module.