Switched-capacitor circuit having a full-wave-rectifying and integrating function

• US 5,142,236 A
• Filed: 10/12/1990
• Issued: 08/25/1992
• Est. Priority Date: 10/16/1989
• Status: Expired due to Fees

• Current Assignee: Marelli Autronica SPA
• Original Assignee: Marelli Autronica SPA
• Inventors: Polito, Gino, Maloberti, Franco, Salerno, Franco
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US07/596,444
• Time in Patent Office: 683 Days
• Field of Search: 307/490, 307/494, 307/262, 307/269, 307/272.1, 307/353, 328/127, 328/26, 328/128
• US Class Current: 327/337
• CPC Class Codes: F02B 1/04 with fuel-air mixture admission into cylinder
• CPC Class Codes: G01R 19/22 using conversion of ac into dc

Abstract

A switched-capacitor circuit is described, which performs the functions of a full-wave rectifier and of an integrator and has a single operational amplifier and a comparator. The circuit is insensitive to the stray capacitances and offsets of the comparator and the operational amplifier. In particular, the input signal is sampled during only one phase of the clock which pilots the operation of the switched-capacitance network.

Claims

1. A circuit for rectifying and integrating an alternating input signal, comprising:

an input terminal,

an operational amplifier,

a first capacitor between the input terminal and the inverting input of the amplifier and a second capacitor between the inverting input and the output of the amplifier,

first and second controlled switches connected between earth and the plate of the first capacitor which faces the input terminal and between the input terminal and the first capacitor, respectively,

third and fourth controlled switches connected in series and in parallel with the second capacitor, respectively,

a clock-signal generator for supplying to the first and second switches respectively first and second clock signals which have the same frequency but which are out of phase so that the respective periods, during which the corresponding switches are closed, alternate and do not overlap, and

control circuit means adapted to supply to the third and fourth switches respective first and second piloting signals which correspond to the first and second clock signals respectively when the input signal has one polarity, but which correspond to the second and first clock signals respectively when the input signal has the opposite polarity,

wherein the control circuit means comprise;

a polarity-determining circuit for providing a logic signal indicative of the polarity of the input signal;

multiplexing circuit means connected to the clock-signal generator means and controlled by the polarity-determining circuit; and

wherein the polarity-determining circuit comprises;

a comparator circuit with an inverting input and a non-inverting input,

a capacitor connected between the input terminal and the inverting input of the comparator circuit,

first and second switches controlled by means of the first and second clock signals respectively and arranged between earth and the plate of the capacitor which faces the input terminal and between the input terminal and the capacitor respectively, and an additional switch piloted by the first clock signal and connected between the inverting input and the output of the comparator circuit.

2. A circuit according to claim 1, wherein the output of the comparator circuit is connected to a D-type flip-flop having a clock input and circuit means connected to the clock input to supply a signal complementary to the second clock signal.

3. A circuit for rectifying and integrating an alternating input signal, comprising:

an input terminal,

an operational amplifier,

a first capacitor between the input terminal and the inverting input of the amplifier and a second capacitor between the inverting input and the output of the amplifier,

first and second controlled switches connected between earth and the plate of the first capacitor which faces the input terminal and between the input terminal and the first capacitor, respectively,

third and fourth controlled switches connected in series and in parallel with the second capacitor, respectively,

fifth and sixth controlled switched connected in parallel and in series with the second capacitor respectively,

a seventh controlled switch connected between the second capacitor and earth;

the fifth and seventh switches being intended to be piloted so as to be open for each time period in which the input signal is integrated, while the sixth switch is intended to be piloted in a complementary manner,

a clock-signal generator for supplying to the first and second switches respectively first and second clock signals which have the same frequency but which are out of phase so that the respective periods, during which the corresponding switches are closed, alternate and do not overlap, and

control circuit means adapted to supply to the third and fourth switches respective first and second piloting signals which correspond to the first and second clock signals respectively when the input signal has one polarity, but which correspond to the second and first clock signals respectively when the input signal has the opposite polarity.