Signal level correction circuit for a video signal
First Claim
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1. A signal processing circuit, comprising:
- an amplifying means having a voltage control amplifier for receiving a video signal comprised of chrominance signals with different signal levels, said amplifier being connected to amplify said video signals with different gains for the respective chrominance signals by supplying DC voltages set in different variable resistors to the control terminal of said voltage control amplifier via switch circuits, and means for selecting the switch circuits synchronously with the chrominance signals and a signal pulse having a width equal to one blanking period;
a first clamp circuit connected to set the black level of the video signal output from said voltage control amplifier comprising means for supplying at every blanking period during one horizontal scanning period;
a peak voltage holding means comprising a comparator having a non-inverting input terminal connected to a capacitor, one terminal of the capacitor being grounded, the comparator having an inverting input terminal connected to a reference voltage source, said comparator being responsive to the supply at the non-inverting input terminal thereof with an output video signal from an adder via a switch which is on/off-controlled with said control signal pulse to said first clamp circuit, for delivering to said adder, via an integration circuit, an output voltage proportional to the difference between the discharge voltage of said capacitor which holds the peak value of noise level in the horizontal blanking period of said video signal as a charge voltage, and the voltage from said reference voltage source;
an adder connected to receive a video signal which has a black level clamped by said first clamp circuit and a peak value provided from said peak holding means, for correcting the black level of said video signal;
a second clamp circuit connected to receive the video signal from said adder via a second amplifier, and to reset the black level of said video signal with said control signal pulse;
a γ
correction circuit connected to correct the γ
value of the video signal from said second clamp circuit;
a clipping circuit connected to clip the dynamic ranges between the white and black levels of said γ
-corrected video signal to a predetermined range;
a third clamp circuit connected to reset the black level of the video signal from said clipping circuit with said control signal pulse; and
an A/D conversion circuit connected to covert the video signal from said third clamp circuit from an analog signal to a digital signal.
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Abstract
A signal level correction circuit for a video signal includes a voltage control amplifier for amplifying a video signal received from a solid state image sensor with different gains for the respective chrominance signals, a first clamp circuit for setting a black level in the video signal received from the amplifier, a comparator for outputting a voltage proportional to the difference between a peak holding voltage of a capacitor in the horizontal blanking period of the video signal clamped by the first clamp circuit, and a reference voltage. An adder adds the output voltage from the comparator and the video signal from the first clamp circuit. A second clamp circuit resets the black level of the amplified video signal. A γ correction circuit adjusts the γ value of the video signal from the second clamp circuit. A clipping circuit clips the dynamic ranges between the white and black level of the γ value corrected video signal. A third clamp circuit resets the black level of the video signal from the clipping circuit. An A/D converter converts the analog video signal into a digital signal.
45 Citations
1 Claim
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1. A signal processing circuit, comprising:
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an amplifying means having a voltage control amplifier for receiving a video signal comprised of chrominance signals with different signal levels, said amplifier being connected to amplify said video signals with different gains for the respective chrominance signals by supplying DC voltages set in different variable resistors to the control terminal of said voltage control amplifier via switch circuits, and means for selecting the switch circuits synchronously with the chrominance signals and a signal pulse having a width equal to one blanking period; a first clamp circuit connected to set the black level of the video signal output from said voltage control amplifier comprising means for supplying at every blanking period during one horizontal scanning period; a peak voltage holding means comprising a comparator having a non-inverting input terminal connected to a capacitor, one terminal of the capacitor being grounded, the comparator having an inverting input terminal connected to a reference voltage source, said comparator being responsive to the supply at the non-inverting input terminal thereof with an output video signal from an adder via a switch which is on/off-controlled with said control signal pulse to said first clamp circuit, for delivering to said adder, via an integration circuit, an output voltage proportional to the difference between the discharge voltage of said capacitor which holds the peak value of noise level in the horizontal blanking period of said video signal as a charge voltage, and the voltage from said reference voltage source; an adder connected to receive a video signal which has a black level clamped by said first clamp circuit and a peak value provided from said peak holding means, for correcting the black level of said video signal; a second clamp circuit connected to receive the video signal from said adder via a second amplifier, and to reset the black level of said video signal with said control signal pulse; a γ
correction circuit connected to correct the γ
value of the video signal from said second clamp circuit;a clipping circuit connected to clip the dynamic ranges between the white and black levels of said γ
-corrected video signal to a predetermined range;a third clamp circuit connected to reset the black level of the video signal from said clipping circuit with said control signal pulse; and an A/D conversion circuit connected to covert the video signal from said third clamp circuit from an analog signal to a digital signal.
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Specification
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Current AssigneeFuji Photo Optical Co. Ltd (Fujifilm Holdings Corporation)
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Original AssigneeFuji Photo Optical Co. Ltd (Fujifilm Holdings Corporation)
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InventorsSuzuki, Shigeo, Okada, Fujio
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Primary Examiner(s)Britton, Howard W.
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Assistant Examiner(s)VU, KIM Y
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Application NumberUS07/629,498Time in Patent Office616 DaysField of Search358/34, 358/32, 358/171, 358/172US Class Current348/677CPC Class CodesH04N 9/72 for reinsertion of DC and s...
