Method and means for transferring a data payload from a first SONET signal to a SONET signal of different frequency

• US 5,142,529 A
• Filed: 07/27/1990
• Issued: 08/25/1992
• Est. Priority Date: 12/09/1988
• Status: Expired due to Term

• Current Assignee: Transwitch Corporation
• Original Assignee: Transwitch Corporation
• Inventors: Upp, Daniel C., Parruck, Bidyut
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Marcelo, Melvin
• Application Number:
  US07/559,636
• Time in Patent Office: 760 Days
• Field of Search: 370/4, 370/84, 370/99, 370/100.1, 370/102, 370/105.3, 370/108, 375/118, 359/115, 359/118, 359/135
• US Class Current: 370/545
• CPC Class Codes: G06F 2205/123 Contention resolution, i.e. resolving conflicts between simultaneous read and write operations
• CPC Class Codes: G06F 5/12 Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
• CPC Class Codes: H04J 3/0623 Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
• CPC Class Codes: H04J 3/1611 Synchronous digital hierarchy [SDH] or SONET H04J3/1664 takes precedence for interactions with OTN
• CPC Class Codes: H04L 25/05 Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
• CPC Class Codes: Y10S 370/907 Synchronous optical network, SONET

Abstract

An apparatus and method for transferring a data payload (SPE) from a first substantially SONET signal into a second substantially SONET signal of different frequency is provided. The apparatus has: a circuit for extracting the SPE from the first SONET signal and sending the bytes of the SPE, according to a first clock, to a FIFO for storage; a circuit for obtaining the SPE bytes from the FIFO according to a second clock, for building the SPE into the second substantially SONET signal; and a circuit for comparing the relative byte phases of the first and second clocks. The byte phase comparison circuit serves two functions. In order to avoid read/write conflicts in the FIFO, it generates and sends a signal to the extracting circuit which causes the extracting circuit to change the byte phase (i.e. timing) at which bytes are sent to the FIFO. Also, in order to adjust the SPE for frequency differences between the first and second substantially SONET signals, the byte phase comparison circuits sends a signal to the circuit which builds the second substantially SONET signal when the two SONET signals have slipped a byte relative to each other. In response thereto, the second substantially SONET signal building circuit generates a negative or positive stuff.

Claims

1. Apparatus for transferring a data payload (SPE) from a first substantially SONET signal having an accompanying clock signal of a first frequency into a second substantially SONET signal having an accompanying clock signal of different frequency, comprising:

(a) means for extracting a first data payload from said first substantially SONET signal, said first data payload comprised of a plurality of bytes, each byte having a plurality of bits, and for forwarding a first timing signal indicative of a byte phase of said first data payload bytes;

(b) a data storage means coupled to said means for extracting into which said bytes of said first data payload are loaded;

(c) data write means coupled to at least one of said means for extracting and said storage means for causing the bytes of said first data payload to be written from said means for extracting into said storage means;

(d) means for building said second substantially SONET signal coupled to said storage means, said second substantially SONET signal having a second data payload comprised of said first data payload bytes, said second data payload having its accompanying clock dictated by an external clock coupled to said means for building, said means for building including means for forwarding a second timing signal indicative of a byte phase of said second data payload bytes;

(e) data read means coupled to said external clock and to at least one of said storage means and said means for building, for causing the first data payload in the storage means to be read at at least one predetermined byte phase of said external clock from the storage means into the means for building, said first data payload thereby constituting said second data payload;

(f) means for measuring indications of the length of time between the occurrences of said first and second timing signals and for generating first signals in response thereto, said means for measuring coupled to said means for forwarding a first timing signal and said means for forwarding a second timing signal, said means for measuring also including means for tracking changes in said measured indications and for generating second signals in response thereto, wherein at least one of said data write means and said data read means is responsive to said first signals generated by said means for measuring and writes or reads said first data payload bytes into or out of said storage means accordingly, and said means for building is responsive to said second signals generated by said means for tracking changes.

2. An apparatus according to claim 1, wherein:

said indications of the length of time between occurrences are indications of a relative byte phase difference between said first and second substantially SONET signals.

3. An apparatus according to claim 2, wherein:

said means for measuring indications is a start/stop counter which counts a number of clock cycles of one of said accompanying clocks between the occurrences of said first and second timing signals.

4. An apparatus according to claim 3, wherein:

said start/stop counter counts the number of clock cycles of said clock accompanying said first substantially SONET signal between a time related to the first clock cycle after said second timing signal to a time related to the clock cycle of said first timing signal.

5. An apparatus according to claim 2, wherein:

said first signals generated in response to said relative byte phase difference between said first and second substantially SONET signals include

a write at a first desired byte phase signal when said relative byte phase difference is greater than or equal to a first desired value, and

a write at a second desired byte phase signal when said relative byte phase difference is less than said first desired value,

wherein said write at a first desired byte phase signal and said write at a second desired byte phase signal cause said data write means to cause payload data to be written into said storage means at different times than said data read means causes payload data to be read.

6. An apparatus according to claim 1, wherein

said means for tracking includes means for storing a previous said indication of the length of time between the occurrences of a previous set of said first and second timing signals, and means for generating said second signals when the stored previous indication of the length of time and a current indication of the length of time between the occurrences of a current set of said first and second timing signals differ in value.

7. An apparatus according to claim 6, wherein:

said means for generating said second signals generates said second signals only when said current and previous indications of the length of time differ, and one of said current and previous indications is at a predetermined value.

8. An apparatus according to claim 7, wherein:

said means for generating said second signals generates a second signal indicative of the need for the amount of data in said storage means to be decreased when said previous indication of the length of time is greater than said current indication of the length of time, and said means for generating said second signals generates a second signal indicative of the need for the amount of data in said storage means to be increased when said previous indication of the length of time is smaller than said current indication of the length of time.

9. An apparatus according to claim 7, wherein:

said means for generating said second signals comprises a plurality of logic gates having indications of said current and previous indications of the length of time as inputs.

10. An apparatus according to claim 8, wherein:

said indications of the length of time between occurrences are indications of a relative byte phase difference between said first and second substantially SONET signals, and

said means for measuring indications is a start/stop counter which counts a number of clock cycles of one of said accompanying clocks between said the occurrences of said first and second timing signals.

11. An apparatus according to claim 10, wherein:

said first signals generated in response to said relative byte phase difference between said first and second SONET signals include

a write at a first desired byte phase signal when said relative byte phase difference is greater than or equal to a first desired value, and

a write at a second desired byte phase signal when said relative byte phase difference is less than said first desired value,

wherein said write at a first desired byte phase signal and said write at a second desired byte phase signal cause said data write means to cause payload data to be written into said storage means at different times than said data read means causes payload data to be read.

12. An apparatus according to claim 1, wherein:

said means for building further comprises pointer generation means for generating pointers pointing to the location in said second substantially SONET signal of the data payload, and payload request means coupled to said data read means for causing said data read means to cause said data payload to be read from said data storage means.

13. An apparatus according to claim 8, wherein:

said means for building further comprises pointer generation means for generating pointers pointing to the location in said second substantially SONET signal of the data payload, and payload request means coupled to said data read means for causing said data read means to cause said data payload to be read from said data storage means,

said payload request means being responsive to said second signals, such that when a second signal indicative of the need for the amount of data in said storage means to be increased is received, said payload request means retards the SPE phase by one byte, and when a second signal indicative of the need for the amount of data in said storage means to be decreased is received, said payload request means advances the SPE phase by one byte.

47. An apparatus according to claim 12 wherein:

said means for extracting determines which of said plurality of bytes of said first data payload is the first (Jl) byte of said first data payload and generates an indication of the same,

said data write means further causes said indication of said first byte of said first data payload to be written to said data storage means along with said first byte of said first data payload,

said data read means reads said indication of said first byte of said first data payload together with said first byte of said first data payload to said means for building, and

said pointer generation means utilizes said indication of said first byte in generating pointers pointing to the location in said second substantially SONET signal of the data payload.

14. A method for transferring a data payload (SPE) from an incoming first substantially SONET signal having an accompanying clock signal of a first frequency into an outgoing second substantially SONET signal having an accompanying clock signal of different frequency, comprising:

(a) receiving said first substantially SONET signal, and extracting a first data payload from said first substantially SONET signal, said first data payload comprised of a plurality of bytes, and forwarding said first data payload to a data storage means;

(b) generating a first timing signal indicative of the phase of the bytes of said first substantially SONET signal;

(c) obtaining said bytes of said first data payload from said storage means in accord with said accompanying clock of said second substantially SONET signal in order to build said second substantially SONET signal, said accompanying clock of said second substantially SONET signal dictated by an external clock;

(d) generating a second timing signal indicative of the phase of the bytes of said second substantially SONET signal;

(e) measuring an indication of the length of time between the occurrences of said first and second timing signals, said indication providing an indication of the byte phase difference between said first and second substantially SONET signals;

(f) changing one of the phase at which the bytes of said first data payload are forwarded to said data storage means and the phase at which the bytes in said storage means are obtained from said storage means when the indication of byte phase difference indicates that said bytes are being forwarded and obtained from said data storage means undesirably closely in time.

15. A method according to claim 14, wherein:

said step of measuring an indication of the length of time comprises starting a counter at the occurrence of one of said first and second timing signals, and stopping the counter at the occurrence of the other of said first and second timing signals.

16. A method according to claim 15, wherein:

said steps of forwarding said first data payload and changing the phase comprise forwarding said first data payload at a first desired phase when said indication of a phase difference is greater than or equal to a first desired value, and forwarding said first data payload at a second desired phase when said indication of a phase difference is less than said first desired value

17. A method according to claim 14, further comprising:

(g) tracking changes in said measured indications, generating second signals in response thereto, and building said second substantially $ONET signal in accord with said second signals.

18. A method according to claim 17, wherein

said step of tracking comprises storing a previous said indication of the length of time between the occurrences of a previous set of said first and second timing signals, and generating said second signals when the stored previous indication of the length of time and a current indication of the length of time between the occurrences of a current set of said first and second timing signals differ in value.

19. A method according to claim 18, wherein

said step of generating said second signals comprises generating said second signals only when said current and previous indications of the length of time differ, and one of said current and previous indications is at a predetermined value.

20. A method according to claim 19, wherein

said step of generating said second signals comprises generating a second signal indicative of the need for the amount of data in said storage means to be decreased when said previous indication of the length of time is greater than said current indication of the length of time, and generating a second signal indicative of the need for the amount of data in said storage means to be increased when said previous indication of the length of time is smaller than said current indication of the length of time

21. A method according to claim 17, wherein:

said step of building said second substantially SONET signal in accord with said second signals comprises generating a pointer for pointing to the location in said second substantially SONET signal of the data payload, adjusting said pointer based on said second signals, and adjusting the location of bytes obtained in said obtaining step in said second substantially SONET signal in building said second substantially SONET signal.

22. A method according to claim 21, wherein:

said stop of adjusting the location of bytes comprises inserting stuff in the byte after the H3 byte of the second substantially SONET signal when said second signal is indicative of the need for the amount of data in said storage means to be increased, and inserting data in the H3 byte of the second substantially SONET signal when said second signal is indicative of the need for the amount of data in said storage means to be decreased.

23. A method according to claim 17, wherein:

said step of measuring an indication of the length of time comprises starting a counter at the occurrence of one of at the occurrence of the other of said first and second timing signals, and

said steps of forwarding said first data payload and changing the phase comprise forwarding said first data payload at a first desired phase when said indication of a phase difference is greater than or equal to a first desired value, and forwarding said first data payload at a second desired phase when said indication of a phase difference is less than said first desired value.

24. A method according to claim 20, wherein:

said step of measuring an indication of the length of time comprises starting a counter at the occurrence of one of said first and second timing signals, and stopping the counter at the occurrence of the other of said first and second timing signals, and

said steps of forwarding said first data payload and changing the phase comprise forwarding said first data payload at a first desired phase when said indication of a phase difference is greater than or equal to a first desired value, and forwarding said first data payload at a second desired phase when said indication of a phase difference is less than said first desired value.

25. A method according to claim 22, wherein:

said step of measuring an indication of the length of time comprises starting a counter at the occurrence of one of said first and second timing signals, and stopping the counter at the occurrence of the other of said first and second timing signals, and

said steps of forwarding said first data payload and changing the phase comprise forwarding said first data payload at a first desired phase when said indication of a phase difference is greater than or equal to a first desired value, and forwarding said first data payload at a second desired phase when said indication of a phase difference is less than said first desired value.

48. A method according to claim 21, further comprising:

determining which of said plurality of bytes of said first data payload is the first (Jl) byte of said first data payload and generating an indication of the same, and forwarding said indication of said first byte of said first data payload to said data storage means along with said first byte of said first data payload,

obtaining said indication of said first byte of said first data payload together with said first byte of said first data payload and utilizing said indication in said step of generating a pointer.

26. Apparatus for transferrinq a data payload (SPE) from a first substantially SONET signal having an accompanying first clock signal of a first frequency into a second substantially SONET signal having a second accompanying clock signal of different frequency, comprising:

(a) a storage means for storing SPE bytes;

(b) means for extracting the bytes of an SPE from the first substantially SONET signal and sending said bytes at at least one predetermined byte phase of the first clock signal to said storage means for storage, said means for extracting being coupled to said storage means;

(c) means for obtaining the SPE bytes from said storage means at at least one predetermined byte phase of the second clock signal including means for building said second substantially SONET signal, said means for obtaining being coupled to said storage means; and

(d) means for comparing the times at which said means for extracting sends said bytes to said storage means and said means for obtaining obtains said bytes from said storage means, said means for comparing being coupled to said means for extracting and said means for obtaining, and said means for comparing including first signalling means for signalling one of said means for extracting and said means for obtaining to change the byte phase at which it sends or obtains said bytes to or from said storage means when said bytes are sent and obtained from said storage means undesirably closely in time.

27. An apparatus according to claim 26, wherein:

said means for comparing further comprises second signalling means for signalling said means for building that one of said first and second substantially $ONET signals has slipped relative to the other of said first and second substantially $ONET signals, and said means for building includes means for generating a negative or positive stuff in response to a signal of said second signalling means

28. An apparatus according to claim 27, wherein:

said means for comparing times is a start/stop counter providing a count.

29. An apparatus according to claim 28, wherein:

said first signalling means signals said means for extracting to send a byte of said SPE of said first substantially SONET signal at a first desired byte phase when said count is greater than or equal to a first desired value, and said first signalling means signals said means for extracting to send a byte of said SPE of said first substantially SONET signal at a second desired byte phase when said count is less than said first desired value,

wherein by sending said bytes of said SPE of said first substantially SONET signal at a first desired byte phase signal and at a second desired byte phase signal, said bytes of said first substantially SONET signal are sent to said storage means at different times than said means for obtaining obtains said bytes.

30. Apparatus for transferring a first data payload from a first data signal having an accompanying clock signal of a first frequency into a substantially SONET signal having an accompanying clock signal of different but similar frequency to said first data signal, said first data payload comprising a plurality of bytes, each byte having a plurality of bits, comprising:

(a) means for obtaining a first timing signal indicative of a byte phase of said first data payload bytes;

(b) a data storage means for receiving said bytes of said first data payload;

(c) data write means for causing the bytes of said first data payload to be written into said storage means;

(d) means for building said second substantially SONET signal coupled to said storage means, said second substantially SONET signal having a second data payload comprised of said first data payload bytes, said second data payload having its accompanying clock dictated by an external clock coupled to said means for building, said means for building including means for forwarding a second timing signal indicative of a byte phase of said second data payload bytes;

(e) data read means coupled to said external clock and to at least one of said storage means and said means for building, for causing the first data payload in the storage means to be read at at least one predetermined byte phase of said external clock from the storage means into the means for building, said first data payload thereby constituting said second data payload;

(f) means for measuring indications of the length of time between the occurrences of said first and second timing signals and for generating first signals in response thereto, said means for measuring coupled to said means for obtaining a first timing signal and said means for forwarding a second timing signal, said means for measuring also including means for tracking changes in said measured indications and for generating second signals in response thereto, wherein at least one of said data write means and said data read means is responsive to said first signals generated by said means for measuring and writes or reads said first data payload bytes into or out of said storage means accordingly, and said means for building is responsive to said second signals generated by said means for tracking changes.

31. An apparatus according to claim 30, wherein:

said indications of the length of time between occurrences are indications of a relative byte phase difference between said first and second substantially SONET signals.

32. An apparatus according to claim 31, wherein:

said means for measuring indications is a start/stop counter which counts a number of clock cycles of one of said accompanying clocks between the occurrences of said first and second timing signals.

33. An apparatus according to claim 32, wherein:

said start/stop counter counts the number of clock cycles of said clock accompanying said first substantially SONET signal between a time related to the first clock cycle after said second timing signal to a time related to the clock cycle of said first timing signal.

34. An apparatus according to claim 31, wherein:

said first signals generated in response to said relative byte phase difference between said first data signal and said substantially SONET signal include

a write at a first desired byte phase signal when said relative byte phase difference is greater than or equal to a first desired value, and

a write at a second desired byte phase signal when said relative byte phase difference is less than said first desired value,

wherein said write at a first desired byte phase signal and said write at a second desired byte phase signal cause said data write means to cause payload data to be written into said storage means at different times than said data read means causes payload data to be read

35. An apparatus according to claim 30, wherein:

said means for tracking includes means for storing a previous said indication of the length of time between the occurrences of a previous set of said first and second timing signals, and means for generating said second signals when the stored previous indication of the length of time and a current indication of the length of time between the occurrences of a current set of said first and second timing signals differ in value.

36. An apparatus according to claim 35, wherein:

said means for generating said second signals generates said second signals only when said current and previous indications of the length of time differ, and one of said current and previous indications is at a predetermined value.

37. An apparatus according to claim 36, wherein:

said means for generating said second signals generates a second signal indicative of the need for the amount of data in said storage means to be decreased when said previous indication of the length of time is greater than said current indication of the length of time, and said means for generating said second signals generates a second signal indicative of the need for the amount of data in said storage means to be increased when said previous indication of the length of time is smaller than said current indication of the length of time.

38. An apparatus according to claim 36, wherein:

said means for generating said second signals comprises a plurality of logic gates having indications of said current and previous indications of the length of time as inputs.

39. An apparatus according to claim 37, wherein:

said indications of the length of time between occurrences are indications of a relative byte phase difference between said first data signal and said substantially SONET signal, and

said means for measuring indications is a start/stop counter which counts a number of clock cycles of one of said accompanying clocks between said the occurrences of said first and second timing signals.

40. An apparatus according to claim 39, wherein:

said first signals generated in response to said relative byte phase difference between said first data signal and said substantially SONET signals include

a write at a first desired byte phase signal when said relative byte phase difference is greater than or equal to a first desired value, and

a write at a second desired byte phase signal when said relative byte phase difference is less than said first desired value,

wherein said write at a first desired byte phase signal and said write at a second desired byte phase signal cause said data write means to cause payload data to be written into said storage means at different times than said data read means causes payload data to be read.

41. An apparatus according to claim 30, wherein:

said means for building further comprises pointer generation means for generating pointers pointing to the location in said substantially SONET signal of the data payload, and payload request means coupled to said data read means for causing said data read means to cause said data payload to be read from said data storage means.

42. An apparatus according to claim 37, wherein:

said means for building further comprises pointer generation means for generating pointers pointing to the location in said substantially SONET signal of the data payload, and payload request means coupled to said data read means for causing said data read means to cause said data payload to be read from said data storage means,

said payload request means being responsive to said second signals, such that when a second signal indicative of the need for the amount of data in said storage means to be increased is received, said payload request means retards the SPE phase by one byte, and when a second signal indicative of the need for the amount of data in said storage means to be decreased is received, said payload request means advances the SPE phase by one byte.

49. An apparatus according to claim 41, wherein:

said means for obtaining obtains an indication of which of said plurality of bytes of said data payload is the first byte of said data payload,

said data write means writes said indication of said first byte of said data payload to said data storage means along with said first byte of said data payload,

said data read means reads said indication of said first byte of said data payload together with said first byte of said data payload to said means for building, and

said pointer generation means utilizes said indication of said first byte in generating pointers pointing to the location in said substantially SONET signal of the data payload.

43. A method for transferring a data payload from a first data signal having an accompanying clock signal of a first frequency into an outgoing substantially SONET signal having an accompanying clock signal of different but similar frequency to said clock signal of said first data signal, comprising:

(a) forwarding said data payload of said first data signal to a data storage means;

(b) generating a first timing signal indicative of the phase of the bytes of said first data signal;

(c) obtaining said bytes of said data payload from said storage means in accord with said accompanying clock of said substantially SONET signal in order to build said substantially SONET signal, said accompanying clock of said substantially SONET signal dictated by an external clock;

(d) generating a second timing signal indicative of the phase of the bytes of said second substantially SONET signal;

(e) measuring an indication of the length of time between the occurrences of said first and second timing signals, said indication providing an indication of the byte phase difference between said first and second substantially SONET signals;

(f) changing one of the phase at which the bytes of said data payload are forwarded to said data storage means and the phase at which the bytes in said storage means are obtained from said storage means when the indication of byte phase difference indicates that said bytes are being forwarded and obtained from said data storage means undesirably closely in time; and

(g) tracking changes in said measured indications, generating second signals in response thereto, and building said substantially SONET signal in accord with said second signals.

44. A method according to claim 43, wherein:

said step of tracking comprises storing a previous said indication of the length of time between the occurrences of a previous set of said first and second timing signals, and generating said second signals when the stored previous indication of the length of time and a current indication of the length of time between the occurrences of a current set of said first and second timing signals differ in value and one of said current and previous indications is at a predetermined value.

45. A method according to claim 44, wherein:

said step of generating said second signals comprises generating a second signal indicative of the need for the amount of data in said storage means to be decreased when said previous indication of the length of time is greater than said current indication of the length of time, and generating a second signal indicative of the need for the amount of data in said storage means to be increased when said previous indication of the length of time is smaller than said current indication of the length of time.

46. A method according to claim 45, wherein:

said step of building said substantially SONET signal in accord with said second signals comprises generating a pointer for pointing to the location in said substantially SONET signal of the data payload, adjusting said pointer based on said second signals, and adjusting the location of bytes obtained in said obtaining step in said substantially SONET signal in building said second substantially SONET signal.