Multipart memory apparatus with error detection
First Claim
1. A memory apparatus for storing and providing retrieval of multiple-bit digital data words, the apparatus comprisingmemory array means for selectively storing the data words, said memory array means being partitioned into a set of bins for storing the words, each said bin including an array of memory cells capable of storing at least one bit, each memory cell having a number of memory cell ports,external data port means, in communication with the memory array means, for receiving at least one of (i) words to be stored in the memory array means or (ii) words to be retrieved from the memory array means, said external data port means having a number of external ports, the number of external ports being greater than the number of memory cell ports of a single memory cell,control means, in communication with said memory array means, for receiving first external signals representative of requests, asserted by an external port, to execute at least one of (i) storing a word in the memory array means or (ii) retrieving a word stored in the memory array means,address decoding means, in communication with said memory array means and said control means, for receiving second external signals representative of external memory address values designating words to be either stored in or retrieved from said memory array means, and converting said second external signals into internal bin addresses designating a plurality of selected bins in which bits of a word are to be either stored or retrieved, said address decoding means includingbin address calculation means, responsive to bit-position values of the bits of each word to be either stored or retrieved, for calculating said bin addresses in accordance with a predetermined bit distribution pattern, to distribute the bits into selected bins, such that requests to retrieve a given data word result in a limited number of bin reading conflicts, the number of bin reading conflicts associated with each word being less than the number of bits in each word, anderror correction means, in communication with the memory array means, for receiving words retrieved from the memory array means and correcting errors in each word resulting from bin reading conflicts, to provide substantially error-free output words.
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Abstract
A memory apparatus for storage and retrieval of digital data is disclosed, including a controller and a memory element having an array of memory cells, each cell having fewer ports than are provided by the memory system. The memory cells are adapted for storing digital data words, each word being a set of bits or symbols. The memory array is partitioned into a plurality of bins for storing words, the individual bits of each word being distributed in a selected addressing sequence among a plurality of selected bins in the memory array, such that bin reading conflicts generate a number of errors less than or equal to a numerical error limit K, where K is less than the number of bits in a word. The data words can be manipulated so as to produce error-free results.
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Citations
11 Claims
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1. A memory apparatus for storing and providing retrieval of multiple-bit digital data words, the apparatus comprising
memory array means for selectively storing the data words, said memory array means being partitioned into a set of bins for storing the words, each said bin including an array of memory cells capable of storing at least one bit, each memory cell having a number of memory cell ports, external data port means, in communication with the memory array means, for receiving at least one of (i) words to be stored in the memory array means or (ii) words to be retrieved from the memory array means, said external data port means having a number of external ports, the number of external ports being greater than the number of memory cell ports of a single memory cell, control means, in communication with said memory array means, for receiving first external signals representative of requests, asserted by an external port, to execute at least one of (i) storing a word in the memory array means or (ii) retrieving a word stored in the memory array means, address decoding means, in communication with said memory array means and said control means, for receiving second external signals representative of external memory address values designating words to be either stored in or retrieved from said memory array means, and converting said second external signals into internal bin addresses designating a plurality of selected bins in which bits of a word are to be either stored or retrieved, said address decoding means including bin address calculation means, responsive to bit-position values of the bits of each word to be either stored or retrieved, for calculating said bin addresses in accordance with a predetermined bit distribution pattern, to distribute the bits into selected bins, such that requests to retrieve a given data word result in a limited number of bin reading conflicts, the number of bin reading conflicts associated with each word being less than the number of bits in each word, and error correction means, in communication with the memory array means, for receiving words retrieved from the memory array means and correcting errors in each word resulting from bin reading conflicts, to provide substantially error-free output words.
Specification