Learning system in a neuron computer

• US 5,142,666 A
• Filed: 02/28/1990
• Issued: 08/25/1992
• Est. Priority Date: 03/01/1989
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yoshizawa, Hideki, Kawasaki, Takashi, Tsuchiya, Chikara, Matsuda, Toshiharu, Kato, Hideki, Asakawa, Kazuo, Ishikawa, Katsuya, Tsuzuki, Hiroyuki, Sugiura, Yoshihide, Iciki, Hiroki, Iwamoto, Hiromu, Endoh, Hideichi
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): Davis, George
• Application Number:
  US07/486,644
• Time in Patent Office: 909 Days
• Field of Search: 364/513, 395/24, 395/27
• US Class Current: 706/38
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology

Abstract

A learning system in a neuron computer includes a neural network for receiving an analog signal from a first analog bus through an analog input port in a time divisional manner and performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. A control pattern memory stores a pattern of a signal for controlling the neural network. A sequencer produces an address of the control pattern memory and a weight memory. The weight memory stores weight data of the neural network. A digital control unit controls the neural network, control pattern memory, sequencer, and weight memory, and executes a learning algorithm. The learning system further includes an input control unit provided on the input side of the neural network for selecting an input signal for executing the learning algorithm input from the digital control unit or an analog input signal input from the analog input port.

Claims

1. A learning system in a neuron computer comprising:

a neural network receiving analog signals from a first analog bus through an analog input port in a time divisional manner, obtaining a product of the analog signals and weights and performing a sum-of-the-products operation, and outputting analog output signals to a second analog bus in a time divisional manner;

a control pattern memory, connected to said neural network, for storing a pattern of a signal for controlling said neural network;

a sequencer, connected to said control pattern memory, for producing an address of said control pattern memory to read a control signal to be provided to the neural network and an address of a weight memory to read the weights;

said weight memory, connected to said sequencer and said neural network, for storing weight data of the neural network;

digital control means, connected to said neural network, control pattern memory, sequencer and weight memory, for controlling said neural network, control pattern memory, sequencer, and weight memory, and for executing a learning algorithm; and

input control means, connected to an input side of said neural network and to said digital control means, for selecting an input signal for executing the learning algorithm input from one of a) said digital control means and b) an analog input signal input from said analog input port so that said input signal and analog input signal are applied to said neural network.

2. The learning system according to claim 1, wherein

said input control means comprises

FIFO memory means for storing a learning pattern received from said digital control means and to be learned as weight data for the network in according with an order of the input of the learning pattern;

D/A converting means having an input connected to an output of said FIFO memory means;

address decoding means for decoding a predetermined address from a microprocessor which manages an overall system;

latching means for latching at least one bit of the data from the microprocessor when the predetermined address is designated by an output of the address decoding means;

selection means for selecting either a signal from the analog input port or an output signal from said FIFO memory means corresponding to the input signal to be input to said neural network in accordance with said latch information;

daisy circuit means for performing D/A converting of the data read from said FIFO memory means in accordance with a CSI signal from said control pattern memory when said selection means selects the output of said FIFO memory means and for outputting a CSO signal when the data read out from said FIFO memory means is transmitted to an analog neuron processor; and

means for transmitting the output from said FIFO memory means when a signal designating that said FIFO memory means has become empty is generated from said FIFO memory means.

3. The learning system according to claim 2, wherein

said digital control means calculates an updating quantity of the weight from an error between the output of said neural network produced in response to a respective learning pattern output from said FIFO memory means and a teacher signal or a previous output value so that the error is decreased and the neural network executes the learning algorithm, and

said neural network outputting weight updating quantity of said neural network to the weight memory is repeated until said error becomes small and the digital control means stores the determined weight information in the weight memory.

4. The learning system according to claim 2, wherein said neural network includes an analog neuron processor,

said daisy circuit feeds back said CSO signal to CSI as a signal to be controlled by an empty signal designating that said FIFO memory means is empty, and

said FIFO memory means transmits an output signal to said analog neuron processor through said D/A converter until said FIFO memory means becomes empty.

5. The learning system in a neuron computer according to claim 1, wherein

said neural network, control pattern memory, sequencer, weight memory, digital control means and input control means are formed on one board.

6. The learning system in a neuron computer according to claim 5, wherein

said board comprises a printed circuit board.

9. The learning system according to claim 1 wherein said input control means receives digital data for learning from said digital control means, and converts the digital data to analog values to be applied to said neural network, when said digital control means executes the learning algorithm.

10. The learning system in a neuron computer according to claim 1 wherein said learning algorithm is performed by a back propagation method in which a difference between an output signal and a teacher signal is subject to back propagation, and weight of the neural network is determined so that the difference is minimized.

11. The learning system in a neuron computer according to claim 1 wherein said digital control means provides digital data for learning to the input control means when said digital control means executes the learning algorithm for learning the weight stored in the weight memory, by using the weight of the weight memory, and said input control means applies the received data to the neural network so that the output of the neural network is applied to the digital control means.

7. A learning system in a neuron computer comprising:

a neural network receiving analog signals from a first analog bus through an analog input port in a time divisional manner, obtaining a product of the analog signals and weights and performing a sum-of-the-products operation, and outputting analog output signals in time divisional manner to a second analog bus;

a control pattern memory, connected to said neural network, for storing a pattern of a signal for controlling said neural network;

a sequencer, connected to said control pattern memory, for producing an address of said control pattern memory to read a control signal to be provided to the neural network and an address of a weight memory to read the weights;

said weight memory connected to said sequencer and said neural network, for storing weight data of the neural network; and

digital control means, connected to said neural network, control pattern memory, sequencer and weight memory, for controlling said neural network, control pattern memory, sequencer, and weight memory, and for executing a learning algorithm, and

wherein said neural network, control pattern memory, sequencer, weight memory and digital control means are formed on one board.

8. A learning system in a neuron computer comprising:

a neural network receiving signals from a first bus through an input port in a time divisional manner, obtaining a product of the analog signals and weights and performing a sum-of-the-products operation, and outputting output signals in a time divisional manner to a second bus;

a control pattern memory, connected to said neural network, for storing a pattern of a signal for controlling said neural network;

a sequencer, connected to said control pattern memory, for producing an address of said control pattern memory to read a control signal to be applied to the neural network and an address of a weight memory to read weight;

said weight memory, connected to said sequencer and said neural network, for storing weight data of the neural network;

digital control means, connected to said neural network, control pattern memory, sequencer and weight memory, for controlling said neural network, control pattern memory, sequencer, and weight memory, and for executing a learning algorithm; and

input control means, connected to an input side of said neural network and connected to said digital control means, for selecting an input signal for executing the learning algorithm input from one of a) said digital control means and b) an input signal input from the input port, so that said input signal and analog input signal are supplied to said neural network.