Context switching devices, systems and methods

• US 5,142,677 A
• Filed: 05/04/1989
• Issued: 08/25/1992
• Est. Priority Date: 05/04/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Boutaud, Frederic, Hollander, James F., Ehlig, Peter N.
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): HAUSER, ROBERT
• Application Number:
  US07/347,615
• Time in Patent Office: 1,209 Days
• Field of Search: 384/200, 384/900
• US Class Current: 718/108
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test
• CPC Class Codes: G06F 11/3648 using additional hardware
• CPC Class Codes: G06F 11/3652 in-circuit-emulation [ICE] arrangements
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/462 with multiple register sets

Abstract

A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Claims

1. A data processing device used with a circuit that produces a digital signal to be processed and an interrupt signal indicating that the digital signal is available for processing, the data processing device comprising;

a data bus;

an arithmetic logic unit connected to said data bus;

an accumulator connected between said arithmetic logic unit and said data bus;

a counterpart register, for the accumulator, coupled to the data bus;

switching means, connected to said accumulator and to said counterpart register, for supplying digital values to the accumulator and also for holding a current digital value in the counterpart register upon an occurrence of the interrupt signal while continuing to supply the accumulator with another digital value during an interrupt routine;

a multiplier connected to said data bus;

a product register connected between said multiplier and said arithmetic logic unit;

a product counterpart register connected between said multiplier and said arithmetic logic unit; and

additional switching means, connected to said product register and to said product counterpart register, for supplying digital product values to the product register and holding a current digital product value in the product counterpart register when the interrupt signal occurs, while continuing to supply the product counterpart register with another digital product value from the multiplier during the interrupt routine.

2. A data processing device used with a circuit that produces a digital signal to be processed and an interrupt signal indicating that the digital signal is available for processing, the data processing device comprising:

a data bus;

an arithmetic logic unit connected to said data bus;

an accumulator connected between said arithmetic logic unit and said data bus;

a counterpart register, for the accumulator, coupled to the data bus;

switching means, connected to said accumulator and to said counterpart register, for supplying digital values to the accumulator and also for holding a current digital value in the counterpart register upon an occurrence of the interrupt signal while continuing to supply the accumulator with another digital value during an interrupt routine;

additional processing circuitry connected to said data bus;

a set of first registers interconnecting the data bus, the arithmetic logic unit and the additional processing circuitry;

a set of second register connected to said data bus; and

switching circuitry for connecting the set of second registers respectively to the first registers until the interrupt signal occurs and then temporarily disconnecting the set of second registers from their corresponding first registers when the interrupt signal occurs.

3. A data processing device used with a circuit that produces a digital signal to be processed and an interrupt signal indicating that the digital signal is available for processing, the data processing device comprising:

a set of first registers and a set of second registers; and

a circuit connected to the set of first and second registers, for executing digital signal processing operations by loading and changing values simultaneously in corresponding ones of the first and second registers so that a value is in a particular one of the first registers and the same value is in a corresponding one of the second registers and for responding to the interrupt signal by executing a set of interrupt operations that load and change at least one value in a particular one of the first registers leaving the corresponding one of the second registers unchanged.

4. The data processing device of claim 3 wherein said circuit for executing includes an arithmetic logic unit, wherein the set of first registers includes an accumulator that is supplied with a value from the arithmetic logic unit, and wherein the set of second registers includes a register corresponding to the accumulator.

5. The data processing device of claim 3 wherein said circuit for executing includes a multiplier, connected directly or indirectly to a data bus, and the set of first registers includes a product register supplied with a product from the multiplier and the set of second registers includes a register corresponding to the product register.

6. The data processing device of claim 3 wherein said circuit for executing includes an address arithmetic unit, connected directly or indirectly to a data bus, and the set of first registers includes an index register for supplying an address value to said address arithmetic unit and the set of second registers includes a register corresponding to the index register.