Intercomputer communication control apparatus and method
First Claim
1. Apparatus for effecting communication among plural digital processors including a first processor and a second processor, said first and second processors being coupled to a system bus for communication therebetween, said first processor being a transmitting processor and said second processor being a receiving processor, said transmitting processor having a message to be transmitted to said receiving processor, said apparatus having common memory accessible to all said processors, comprising:
- a pluarlity of mailbox locations corresponding to said plurality of processors, respectively, in said common memory,said mailbox location corresponding to said transmitting processor being utilized only for transfer of messages from said transmitting processor to receiving processors, said transmitting processor utilizing only said mailbox location corresponding thereto for transfer of messages to receiving processors,means in said transmitting processor for generating said message to be transmitted to said receiving processor and for writing said message into said mailbox location corresponding to said transmitting processor, said message including an address signal representative of said receiving processor,awakening means in said transmitting processor for sending a wake-up interrupt signal to said receiving processor to interrupt said receiving processor so as to alert said receiving processor that it has a pending message,polling means in said receiving processor for scanning said mailbox locations in response to said wake-up interrupt signal to find an address signal representative of said receiving processor in a mailbox location, said mailbox location thereby having a message therein addressed to said receiving processor, whereby said receiving processor finds said message in said mailbox location having its address signal therein,wherein said awakening means comprises means for transmitting said wake-up interrupt signal from said first processor to said second processor, said second processor having a wake-up interrupt signal input corresponding thereto, said awakening means comprisingmeans in said first processor for generating and transmitting a first type of instruction having an opcode portion, an address portion and a data portion, andconverting means, through which said second processor is coupled to said system bus, responsive to said first type of instruction for generating said wake-up interrupt signal for transmission to said wake-up interrupt signal input when said opcode portion designates said first type of instruction, said address portion contains the address of said second processor and said data portion contains a data signal representative of said wake-up interrupt signal.
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Accused Products
Abstract
Interprocessor message communication and synchronization apparatus and method for a plurality of processors connected to a system bus. The message communication photocol involves utilizing an array of mailbox locations associated with the processors, respectively, and located in common memory accessible to all of the processors. A processor desiring to send a message to another processor inserts the message into its mailbox along with the address of the other processor. The sending processor interrupts the receiving processor which, in response to the interrupt, scans the mailboxes to find the mailbox with its address therein thereby receiving the message. The interrupt is effected by the sending processor broadcasting an input/output write instruction on the system bus along with the address of the receiving processor and a data field representative of the interrupt to be transmitted. Apparatus associated with the receiving processor includes a decoder that responds to the input/output write instruction to enable a register when the address transmitted on the bus matches its address. The enabled register receives the data signals from the bus to set therein the appropriate interrupt signal represented by the data. The stages of the register are connected to the associated interrupt input of the other processor.
159 Citations
12 Claims
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1. Apparatus for effecting communication among plural digital processors including a first processor and a second processor, said first and second processors being coupled to a system bus for communication therebetween, said first processor being a transmitting processor and said second processor being a receiving processor, said transmitting processor having a message to be transmitted to said receiving processor, said apparatus having common memory accessible to all said processors, comprising:
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a pluarlity of mailbox locations corresponding to said plurality of processors, respectively, in said common memory, said mailbox location corresponding to said transmitting processor being utilized only for transfer of messages from said transmitting processor to receiving processors, said transmitting processor utilizing only said mailbox location corresponding thereto for transfer of messages to receiving processors, means in said transmitting processor for generating said message to be transmitted to said receiving processor and for writing said message into said mailbox location corresponding to said transmitting processor, said message including an address signal representative of said receiving processor, awakening means in said transmitting processor for sending a wake-up interrupt signal to said receiving processor to interrupt said receiving processor so as to alert said receiving processor that it has a pending message, polling means in said receiving processor for scanning said mailbox locations in response to said wake-up interrupt signal to find an address signal representative of said receiving processor in a mailbox location, said mailbox location thereby having a message therein addressed to said receiving processor, whereby said receiving processor finds said message in said mailbox location having its address signal therein, wherein said awakening means comprises means for transmitting said wake-up interrupt signal from said first processor to said second processor, said second processor having a wake-up interrupt signal input corresponding thereto, said awakening means comprising means in said first processor for generating and transmitting a first type of instruction having an opcode portion, an address portion and a data portion, and converting means, through which said second processor is coupled to said system bus, responsive to said first type of instruction for generating said wake-up interrupt signal for transmission to said wake-up interrupt signal input when said opcode portion designates said first type of instruction, said address portion contains the address of said second processor and said data portion contains a data signal representative of said wake-up interrupt signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification