Power conservation in microprocessor controlled devices

• US 5,142,684 A
• Filed: 06/23/1989
• Issued: 08/25/1992
• Est. Priority Date: 06/23/1989
• Status: Expired due to Term

• Current Assignee: Hand Held Products Incorporated (Honeywell International Inc.)
• Original Assignee: Hand Held Products Incorporated (Honeywell International Inc.)
• Inventors: Stant, Vernon L., Perry, Richard A.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Loomis, John C.
• Application Number:
  US07/370,648
• Time in Patent Office: 1,159 Days
• Field of Search: 364/200, 364/900
• US Class Current: 713/320
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Power may be conserved and battery life may be extended in a microprocessor controlled device by providing two microprocessors, one of which is a low power, low performance low speed processor for performing background tasks, the other of which is a high power, high performance, high speed processor for performing computationally intensive foreground tasks. The low speed processor activates the high speed processor when a high performance task is to be performed. When activating the high performance processor, the low performance processor also controls the device'"'"'s power supply to provide high voltage to the high speed processor. The high speed processor may run at variable clock speeds, with power consumption of the processor increasing with increasing speed. The high speed processor selects its own clock speed based upon the task to be performed, by including a clock speed in each software subroutine which controls a task. The software subroutine associated with a task is thereby executed at its associated clock speed, which may be chosen to be the lowest possible clock speed consistent with the task to be performed.

Claims

1. A method for controlling a multiprocessor system including a first processor having a first central processing unit operating under stored program control, and operating at a first speed and at a first power supply voltage or at a second power supply voltage which is greater than said first power supply voltage, and a second processor having a second processing unit operating under store program control, and operating at a second speed which is greater than said first speed, and at said second power supply voltage, and power supplying means for supplying said first or second power supply voltages to said first and second processors, said method comprising the steps of:

operating said first processor at said first speed and at said first power supply voltage;

determining whether a task is to be performed at said second speed;

controlling said power supplying means to provide said second voltage to said first and second processing units if a task is to be performed at said second speed; and

activating said second processor if a task is to be performed at said second speed.

2. The method of claim 1 wherein said controlling step is preceded by the step of determining whether sufficient power is available from said power supplying means to operate said power supplying means at said second power supply voltage if a task is to be performed at said second speed.

3. The method of claim 1 wherein said second speed comprises a plurality of second speeds, and wherein said activating step is followed by the step of:

operating said second processor at one of said plurality of second speeds for performing the task.

4. The method of claim 3 wherein the step of operating said second processor at one of said plurality of second speeds for performing the task comprises the steps of:

identifying the task to be performed at said second speed;

activating a software routine for performing the identified task;

identifying one of said plurality of second speeds associated with the activated software routine; and

operating said second processor at the identified one of said plurality of second speeds for performing the task.

5. The method of claim 3 wherein the step of operating said second processor at one of said plurality of second speeds for performing the task is followed by the step of operating said second processor at a slow one of said plurality of second speeds after said task is performed.

6. The method of claim 1 wherein said activating step is followed by the step of continuing to operate said first processor at said first speed.

7. A method for controlling a multiprocessor system including a first processor having a first central processing unit operating under stored program control, and operating at a first speed and at a first power supply voltage or at a second power supply voltage which is greater than said first power supply voltage, and a second processor having a second central processing unit operating under stored program control, and operating at one of a plurality of second speeds at said second power supply voltage and a power supplying means for supplying said first and second power supply voltages in said first and second processors, said method comprising the steps of:

operating said first processor at said first speed and at said first power supply voltage;

determining whether a task is to be performed by said second processor;

controlling said power supplying means to provide said second voltage to said first and said second processor if a task is to be performed by said second processor;

activating said second processor if a task is to be performed by said second processor;

identifying the task to be performed by said second processor;

initiating execution of a software routine for performing the identified task;

identify one of said plurality of second speeds corresponding with the activated software routine; and

operating said second processor at the identified one of said plurality of second speeds for performing the task.

8. The method of claim 7 wherein said controlling step is proceeded by the step of determining whether sufficient battery power is available to operate said power supplying means at said second power supply voltage if a task is to be performed by said second processor.

9. The method of claim 7 wherein the step of operating said second processor is followed by the step of operating said second processor at a slow one of said plurality of second speeds after said task is performed.

10. A multiprocessor system comprising:

a first processor having a first central processing unit operating under stored program control and operating at a first speed and at a first power supply voltage or at a second power supply voltage which is greater than said first power supply voltage for performing first tasks;

a second processor having a second central processing unit operating under stored program control, and operating at a second speed which is greater than said first speed and at said second power supply voltage, said first processor including means for activating said second processor for performing second tasks at said second speed,

power supplying means for supplying power to said first and second processors; and

power supply control means, connected to said means for activating said second processor and to said power supply means, for controlling said power supplying means to provide said second power supply voltage to said first and second processors when said second processor is activated.

11. The multiprocessor system of claim 10 wherein said first processor consumes a first amount of power and wherein said second processor consumes a second amount of power which is greater than said first amount of power, said means for activating said second processor thereby minimizing power consumption in said multiprocessor system.

12. The multiprocessor system of claim 10 wherein said power supplying means includes a battery.

13. The multiprocessor system of claim 10 wherein said multiprocessor system is portable.

14. The multiprocessor system of claim 10 wherein said multiprocessor system is incorporated into a portable bar code reader.

15. The multiprocessor system of claim 14 further comprising:

a scanner connected to at least one of said first and second processors for reading and decoding bar codes under control of at least one of said first and second processors.

16. The multiprocessor system of claim 14 further comprising:

a keyboard connected to at least one of said first and second processors for accepting user inputs under control of at least one of said first and second processors.

17. The multiprocessor system of claim 14 further comprising:

a display connected to at least one of said first and second processors for displaying user information under control of at least one of said first and second processors.

18. The multiprocessor system of claim 14 further comprising:

a scanner connected to at least one of said first and second processors for reading and decoding bar codes under control of at least one of said first and second processors;

a keyboard connected to at least one of said first and second processors for accepting user inputs under control of at least one of said first and second processors; and

a display connected to at least one of said first and second processors for displaying user information under control of at least one of said first and second processors.

19. The multiprocessor system of claim 10 wherein said first tasks comprise background tasks and wherein said second tasks comprise foreground tasks.

20. The multiprocessor system of claim 19 wherein said background tasks comprise computationally simple tasks and wherein said foreground tasks comprise computationally intensive tasks.

21. The multiprocessor system of claim 10 wherein said first processor includes means for determining that a second task is to be performed;

said means for activating said second processor comprising means for activating said second processor in response to said determining means.

22. The multiprocessor system of claim 10 wherein said first processor continues to operate at said first speed for performing said first tasks when said second processor operates at said second speed for performing said second tasks.

23. The multiprocessor system of claim 10 wherein said power supplying means includes a battery for supplying said first power supply voltage and a switching regulator connected to said battery for supplying said second power supply voltage.

24. The multiprocessor system of claim 10 wherein said second speed comprises a plurality of second speeds greater than said first speed, and wherein said multiprocessor system further comprises:

a variable speed clock, connected to said second processor, for operating said second processor at said plurality of second speeds; and

means for controlling said variable speed clock to operate at said one of said second speeds.

25. The multiprocessor system of claim 24 further comprising:

a plurality of stored program routines for controlling said second processor to perform said second tasks, each of said routines having one of said plurality of second speeds associated therewith; and

means for selecting one of said stored program routines to be performed;

said means for controlling said variable speed clock being responsive to said means for selecting to thereby control said variable speed clock to operate at said one of said second speeds associated with the selected one of said stored program routines.

26. The multiprocessor system of claim 25 wherein said one of said plurality of second speeds associated with a respective one of said plurality of routines comprises the lowest speed with which the associated one of said plurality of tasks may be performed.

27. A multiprocessor system comprising:

a first processor having a first central processing unit operating under stored program control, and operating at a first power supply voltage level or at a second power supply voltage level which is greater than said first power supply voltage level for performing a first task;

a second processor having a second central processing unit operating under stored program control, and operating at said second power supply voltage level for performing a second task;

power supplying means for providing said first power supply voltage level to said first processor and for selectively providing said second power supply voltage level to said second processor; and

means for controlling said power supplying means to provide said second power supply voltage level to said first and second processors when said second task is performed.

28. The multiprocessor system of claim 27 wherein said means for controlling is included in said first processor.

29. The multiprocessor system of claim 27 wherein said power supplying means includes a battery.

30. The multiprocessor system of claim 27 wherein said power supply means includes a battery for supplying said first power supply voltage and a switching regulator connected to said battery for supplying said second power supply voltage.

31. The multiprocessor system of claim 27 wherein said multiprocessor system is portable.

32. The multiprocessor system of claim 27 wherein said multiprocessor system is a portable bar code reader.

33. The multiprocessor system of claim 27 wherein said first processor further comprises means for determining that said second task is to be performed;

said determining means being connected to said means for controlling to thereby activate said second processor when said second task is to be performed.

34. The multiprocessor system of claim 27 further comprising:

a scanner connected to at least one of said first and second processors for reading and decoding bar codes under control of at least one of said first and second processors.

35. The multiprocessor system of claim 27 further comprising:

a keyboard connected to at least one of said first and second processors for accepting user inputs under control of at least one of said first and second processors.

36. The multiprocessor system of claim 27 further comprising:

a display connected to at least one of said first and second processors for displaying user information under control of at least one of said first and second processors.

37. The multiprocessor system of claim 27 further comprising:

a scanner connected to at least one of said first and second processors for reading and decoding bar codes under control of at least one of said first and second processors;

a keyboard connected to at least one of said first and second processors for accepting user inputs under control of at least one of said first and second processors; and

a display connected to at least one of said first and second processors for displaying user information under control of at least one of said first and second processors.

38. The multiprocessor system of claim 27 wherein said first processor operates at a first speed and wherein said second processor operates at a plurality of second speeds greater than said first speed, wherein said task comprises a plurality of second tasks, and wherein said multiprocessor system further comprises:

a variable speed clock connected to said second processor, for operating said second processor at said plurality of second speeds; and

means, responsive to said first processor, for controlling said variable speed clock to operate at one of said second speeds.

39. The multiprocessor system of claim 38 further comprising:

a plurality of stored program routines for controlling said second processor to perform said second tasks, each of said routines having one of said plurality of second speeds associated therewith; and

means for selecting one of said stored program routines to be performed;

said means for controlling said variable speed clock being responsive to said means for selecting to thereby control said variable speed clock to operate at said one of said second speeds associated with the selected one of said stored program routines.

40. The multiprocessor system of claim 38 wherein said one of said plurality of second speeds associated with a respective one of said routines comprises the lowest speed with which the associated one of said plurality of tasks may be performed.

41. The multiprocessor system of claim 27 wherein said first task comprises a background task and wherein said second task comprises a foreground task.

42. The multiprocessor system of claim 41 wherein said background task is a computationally simple task and wherein said foreground task is a computationally intensive task.

43. The multiprocessor system of claim 27 wherein said first operates at said second power supply voltage level for performing said first task while said second processor operates at said second power supply voltage level for performing said second task.

44. A data processing system comprising:

a first stored program processor;

a variable speed clock connected to said first processor, for operating said first processor at a plurality of speeds;

a plurality of stored program routines for controlling said first processor to perform a plurality of tasks;

a second stored program processor, said second processor including means for activating said first processor for performing said plurality of tasks;

a plurality of stored speed data, each of which corresponds to one of said plurality of speeds a respective one of which correspond with a respective one of said stored program routines;

means for selecting one of said stored program routines to be performed and the corresponding one of said stored speed data; and

means for controlling said variable speed clock to operate said first processor at said one of said plurality of which corresponds with the selected one of said stored program routines.

45. The data processing system of claim 44 wherein said one of said plurality of preselected stored speed data which corresponds with a respective one of said routines comprises the lowest speed with which the corresponding one of said plurality of tasks only be performed.

46. The data processing system of claim 44 further comprising means for supplying power to said first processor.

47. The data processing system of claim 44 further comprising battery powered means for supplying power to said first processor.

48. The data processing system of claim 44 wherein said data processing system is portable.

49. The data processing system of claim 44 wherein said data processing system is a portable bar code reader.

50. The data processing system of claim 44 further comprising:

a scanner connected to said first processor for reading and decoding bar codes under control of said first processor.

51. The data processing system of claim 44 further comprising:

a keyboard connected to said first processor for accepting user inputs under control of said first processor.

52. The data processing system of claim 44 further comprising:

a display connected to said first processor for displaying user information under control of said first processor.

53. The data processing system of claim 44 further comprising:

a scanner connected to said first processor for reading and decoding bar codes under control of said first processor;

a keyboard connected to said first processor for accepting user inputs under control of said first processor; and

a display connected to said first processor for displaying user information under control of said first processor.

54. The data processing system of claim 44 wherein said second processor operates at a second speed and wherein said plurality of speeds are greater than said second speed.

55. The data processing system of claim 54 wherein said second processor consumes a second amount of power and wherein said first processor consumes a first amount of power which is directly proportional to the selected one of said plurality of speeds.

56. The data processing system of claim 44 wherein said second processor operates at a first power supply voltage or a second power supply voltage and said first processor operates at a said first power supply voltage;

said data processing system further comprising a power supply for selectively supplying said first power supply voltage to said first processor and said second power supply voltage to said second processor;

said data processing system further comprising power supply control means connected to said means for activating said first processor, for controlling said power supply to provide said first power supply voltage to said first and second processors while said first processor is active.

57. The multiprocessor system of claim 56 wherein said power supply means includes a battery for supplying said first power supply voltage and a switching regulator connected to said battery for supplying said second power supply voltage.

58. A multiprocessor system comprising:

a first processor having a first central processing unit operating under stored program control, and operating at a first speed at a first power supply voltage or at a second power supply voltage which is greater than said first power supply voltage;

a second processor having a second central processing unit operating under stored program control, and operating at a selected one of a plurality of second speeds, at said second power supply voltage;

a power supplying means for providing said first power supply voltage to said first processor and selectively providing said second power supply voltage to said second processor;

means in said first processor for performing background tasks;

means in said first processor for determining that a foreground task is to be performed;

means, responsive to said determining means, for controlling said power supply to provide said second power supply level to said second processor;

means, responsive to said determining means, for activating said second processor to perform foreground tasks;

a plurality of stored program routines for controlling said second processor to perform foreground tasks, each of said routines having one of said plurality of second speeds corresponding therewith;

means for selecting one of said stored program routines to be performed; and

means for operating said second processor at said one of said plurality of speeds corresponding with the selected one of said stored program routines, whereby power consumption in said multiprocessor system is minimized.

59. The multiprocessor system of claim 58 wherein said power supplying means includes a battery.

60. The multiprocessor system of claim 59 wherein said multiprocessor system is a portable multiprocessor system.

61. The multiprocessor system of claim 58 wherein said multiprocessor system is a portable bar code reader.

62. The multiprocessor system of claim 58 further comprising:

a scanner connected to at least one of said first and second processors for reading and decoding bar codes under control of at least one of said first and second processors.

63. The multiprocessor system of claim 58 further comprising:

a keyboard connected to at least one of said first and second processors for accepting user inputs under control of at least one of said first and second processors.

64. The multiprocessor of claim 58 further comprising:

a display connected to at least one of said first and second processors for displaying user information under control of at least one of said first and second processors.

65. The multiprocessor system of claim 58 further comprising:

a scanner connected to at least one of said first and second processors for reading and decoding bar codes under control of at least one of said first and second processors;

a keyboard connected to at least one of said first and second processors for accepting user inputs under control of at least one of said first and second processors; and

a display connected to at least one of said first and second processors for displaying user information under control of at least one of said first and second processors.

66. The multiprocessor system of claim 58 wherein said one of said plurality of second speeds associated with a respective one of said routines comprises the lowest speed with which the associated one of said foreground tasks may be performed.