Programmable logic cell and array

• US 5,144,166 A
• Filed: 11/02/1990
• Issued: 09/01/1992
• Est. Priority Date: 11/02/1990
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Concurrent Logic, Inc. (Microchip Technology Incorporated)
• Inventors: Furtek, Frederick C., Camarota, Rafael C., Ho, Walford W., Browder, Edward H.
• Primary Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US07/608,415
• Time in Patent Office: 669 Days
• Field of Search: 307/465, 307/468, 307/465.1, 307/469, 307/243, 307/303.2, 340/825.83, 340/825.87, 340/825.91
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.

Claims

1. A programmable logic array comprising:

a plurality of logic cells, wherein each cell except those at the edges of the array has four nearest-neighbor cells, one to the left (or West), one to the right (or East), one above (or to the North) and one below (or to the South) so as to form an array in which said logic cells are aligned in rows and columns, each cell comprising;

eight inputs, two from each of its four nearest neighbors,

eight outputs, two to each of its four nearest neighbors,

means for storing a plurality of control bits,

means for multiplexing the eight inputs onto first and second input leads, the inputs connected to said input leads being specified by control bits stored in said storing means, and

logic means for generating signals on said outputs in response to signals on said input leads and control bits stored in said storing means.

2. The apparatus of claim 1 wherein a logic cell receives only two inputs directly from each nearest-neighbor cell and provides only two outputs directly to each nearest-neighbor cell.

3. The apparatus of claim 1 wherein the inputs and outputs associated with the four nearest-neighbor cells are functionally equivalent.

4. The apparatus of claim 1 wherein the logic means implements a pair of Boolean logic functions.

5. The apparatus of claim 1 wherein the logic means implements an exclusive OR and a NAND function.

6. The apparatus of claim 1 wherein the logic means implements a flip-flop.

7. The apparatus of claim 1 wherein the logic means provides a constant logic signal to at least one of the outputs.

8. The apparatus of claim 1 wherein the multiplexing means comprises first and second multiplexers each of which has at least four inputs, each of said four inputs to the first multiplexer coming from a different nearest-neighbor cell and each of said four inputs to the second multiplexer coming from a different one of the same nearest-neighbor cell.

9. The apparatus of claim 1 wherein the logic means has two output leads, one of which fans out to four of said outputs and the other of which fans out to the other four outputs.

10. The apparatus of claim 1 wherein at least three of said cells are connected in cascade with the outputs of a first cell connected to the inputs of a second cell and the outputs of said second cell connected to the inputs of a third cell, whereby when each cell provides an exclusive OR and logical NAND function on its outputs with respect to its inputs the first cell provides at its outputs the exclusive OR and NAND of its inputs, the second cell provides at its outputs the exclusive NOR and NOR of the inputs to the first cell, and the third cell provides at its outputs the AND and the OR of the inputs to the first cell.