SRAM based cell for programmable logic devices

• US 5,144,582 A
• Filed: 03/30/1990
• Issued: 09/01/1992
• Est. Priority Date: 03/30/1990
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Steele, Randy C.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/502,572
• Time in Patent Office: 886 Days
• Field of Search: 365/189.08, 364/716, 307/465, 307/468, 340/825.83
• US Class Current: 365/189.08
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17712 one of the matrices at least being reprogrammable
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters

Abstract

A programmable cell for use in programmable logic devices utilizes CMOS SRAM technology. True and complement cells are paired, and generate a signal which can be combined with other such signals to give a product term. SRAM bits store program information, and drive the generated signal as a function of values at its true and complementary inputs. The generated signal goes through a full CMOS voltage swing, so that no sense amplifiers are required for the product term.

Claims

1. A programmable logic device having a plurality of inputs and a plurality of outputs connected to an AND-OR array for defining logic functions to be performed by the device, comprising:

a plurality of SRAM cells arranged in a regular matrix for storing program information defining connections in the AND-OR array; and

logic gates connecting outputs from selected SRAM cells together to perform logic functions thereon, said logic gates generating outputs which define product terms of the AND-OR array.

2. The device of claim 1, wherein said SRAM cells comprise asymmetrical 5 transistor cells.

3. The device of claim 1, wherein said SRAM cells comprise symmetrical 6 transistor cells.

4. The device of claim 1, wherein said SRAM cells comprise asymmetrical 6 transistor cells, wherein each SRAM cell is programmed using a global program enable signal and a signal supplied to a row signal line corresponding to the cell.

5. The device of claim 1, wherein one of said logic gates combines the output of each SRAM cell with a selected row or complemented row signal.

6. The device of claim 5, wherein each SRAM cell in the matrix has an output connected to a NAND gate, wherein a second input for each NAND gate is connected to a selected row or complementary row signal, and wherein an output of each NAND gate is connected to an input of one of said logic gates.

7. The device of claim 1, wherein said SRAM cells are connected together into pairs of cells having complementary row inputs, wherein the outputs of the cells in each pair are combined into a single signal.

8. The device of claim 7, wherein the single signal outputs of selected cell pairs are combined in said logic gates to generate product term signals.

9. An AND-OR array for a semiconductor integrated circuit programmable logic device, comprising:

a plurality of linear arrays of SRAM cells, each linear array corresponding to a product term of the AND-OR array;

wherein each SRAM cell contains a programming bit defining a connection in the AND-OR array;

a plurality of first logic gates, each of said logic gates connected to at least two of the SRAM cells in a single linear array; and

at least one additional logic gate having inputs connected to outputs of selected first logic gates or to outputs of selected additional logic gates, wherein said additional logic gates combine signals from the SRAM cells so as to generate an output signal which is defined as a product term for each of said linear arrays.

10. The AND-OR array of claim 9, wherein the SRAM cells are grouped into pairs of cells having a common output node, and wherein the common output nodes connect to the inputs of said first logic gates.

11. The AND-OR array of claim 10, wherein the SRAM cells comprise symmetrical 6 transistor cells.

12. The AND-OR array of claim 10, wherein said SRAM cells comprise asymmetrical 6 transistor cells, wherein each SRAM cell is programmed using a global program enable signal and a signal supplied to a row signal line corresponding to the cell.

13. A method for generating product term signals in a semiconductor integrated circuit programmable logic device, comprising the steps of:

storing data in an array of SRAM cells;

providing input signals to the array;

generating output signals from the SRAM cells which are a function of input signals applied thereto and the data stored in the cells; and

combining selected groups of SRAM cell outputs in logic gates to form product term signals.

14. The method of claim 13, wherein the selected groups of SRAM cell outputs selected to form each product term are obtained from SRAM cells located in a single row of the array.

15. The method of claim 14 wherein, within a row of SRAM cells located in a single row of the array, SRAM cells having row and complementary row inputs are paired so as to provide a common output signal, and wherein such common output signals are combined to form the product term signals.

16. The method of claim 13, wherein an SRAM bit in each cell is logically combined with a row or complementary row signal to generate the output signal from the cell.

17. The method of claim 16, wherein the SRAM bit is combined with the row or complementary row signal in a NAND gate.