Apparatus and method for positioning an integrated circuit chip within a multichip module

• US 5,144,747 A
• Filed: 03/27/1991
• Issued: 09/08/1992
• Est. Priority Date: 03/27/1991
• Status: Expired due to Fees

• Current Assignee: Integrated System Assemblies Corp.
• Original Assignee: Integrated System Assemblies Corp.
• Inventors: Eichelberger, Charles W.
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US07/676,938
• Time in Patent Office: 531 Days
• Field of Search: 29/740, 29/833, 29/840, 29/834
• US Class Current: 29/834
• CPC Class Codes: H01L 21/67121 Apparatus for making assemblies not otherwise provided for, e.g. package constructions
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01011 Sodium [Na]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01025 Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10S 977/788 : Of specified organic or carbon-based composition
• CPC Class Codes: Y10S 977/90 : having step or means utilizing mechanical or thermal property, e.g. pressure, heat
• CPC Class Codes: Y10S 977/951 : Laser
• CPC Class Codes: Y10T 29/49131 : by utilizing optical sighting device
• CPC Class Codes: Y10T 29/49133 : with component orienting
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/53178 : Chip component

Abstract

A multichip integrated circuit package comprises a substrate having a flat upper surface to which is affixed one or more integrated circuit chips having interconnection pads. A polymer encapsulant completely surrounds the integrated circuit chips. The encapsulant is provided with a plurality of via openings therein to accommodate a layer of interconnection metallization. The metallization serves to connect various chips and chip pads with the interconnection pads disposed on the chips. In specific embodiments, the module is constructed to be repairable, have high I/O capability with optimal heat removal, have optimized speed, be capable of incorporating an assortment of components of various thicknesses and function, and be hermetically sealed with a high I/O count. Specific processing methods for each of the various module features are described herein, along with additional structural enhancements.

Claims

1. A method for attaching an integrated circuit chip to an upper surface of a substrate having a fiducial mark thereon, said attaching method utilizing a high accuracy XY table, said table having a first rotational adjustment stage and a second rotational adjustment stage, said first rotational adjustment stage comprising a chip alignment stage for holding and aligning a chip relative to XY table motion, said second rotational adjustment stage comprising a substrate alignment stage, said attaching method further utilizing a chip pickup for removing said chip from said chip alignment stage and for placing said chip on said substrate and a memory means containing desired positional offset information for said chip relative to said substrate fiducial mark, said method comprising the steps of:

(a) placing a substrate on said substrate alignment stage, said substrate having an adhesively coated upper surface;

(b) aligning said substrate relative to XY table motion;

(c) locating and saving in said memory means the position of the fiducial mark on said substrate;

(d) placing a chip on said chip alignment stage;

(e) aligning said chip relative to XY table motion, said chip aligning being accomplished with reference to a characteristic feature of said chip;

(f) energizing said chip pickup to lift said chip from said die alignment stage;

(g) positioning said substrate under said chip by moving said XY table;

(h) recalling from said memory means the stored offset for said chip relative to said fiducial mark on said substrate;

(i) lowering said chip to a desired location on the upper surface of said substrate based on said recalled, chip offset location, and allowing a portion of the weight of said chip pickup to be applied to said chip;

(j) holding said chip pickup against said chip for a period of time to allow said chip to adhesively attach to said substrate; and

(k) releasing said chip from said chip pickup.

2. The chip attach method of claim 1, wherein multiple chips are to be attached to the upper surface of said substrate, and said method further comprises repeating said steps (d)-(k) for each of said multiple chips to be attached to said substrate.

3. The chip attach method of claim 1, further comprising the step of locating the center of each chip, and wherein said chip pickup energized in said step (f) lifts said chip relative to said located chip center.

4. A method for attaching a first and second integrated circuit chips to an upper surface of a substrate having a reference feature thereon, said attaching method utilizing a high accuracy XY table, said table having a first rotational adjustment stage and a second rotational adjustment stage, said first rotational adjustment stage comprising a chip alignment stage and said second rotational adjustment stage comprising a substrate alignment stage, said attaching method further utilizing a chip pickup and memory storage means having at least a prestored desired location information for said second chip relative to a reference feature of said first chip, said method comprising the steps of:

(a) placing the substrate on said substrate alignment stage, said substrate having an adhesively coated upper surface;

(b) aligning said substrate relative to XY table motion;

(c) locating and saving in said memory means the position of the substrate reference feature;

(d) placing the first chip on said chip alignment stage;

(e) aligning said first chip relative to XY table motion, said first chip aligning being accomplished with reference to at least one reference feature of said first chip;

(f) energizing said chip pickup to lift said first chip from said chip alignment stage;

(g) positioning said substrate under said first chip by moving said XY table;

(h) recalling from said memory means the stored offset for said first chip relative to said substrate reference feature;

(i) lowering said first chip to the desired location on the upper surface of said substrate based on said recalled, first chip offset location, and allowing a portion of the weight of said chip pickup to be applied to said first chip;

(j) releasing said first chip from said chip pickup;

(k) placing the second chip on said chip alignment stage;

(l) aligning said second chip relative to XY table motion, said second chip aligning being accomplished with reference to at least one characteristic feature of said second chip;

(m) energizing said chip pickup to lift said second chip from said chip alignment stage;

(n) positioning said substrate under said second chip by moving said XY table;

(o) recalling from said memory means the prestored desired location information for said second chip relative to a reference feature of said first chip;

(p) lowering said second chip to the desired location on the upper surface of said substrate based on said recalled, second chip offset location, and allowing a portion of the weight of said chip pickup to be applied to said second chip; and

(q) releasing said second chip from said pickup.

5. The chip attach method of claim 4, wherein said steps (k)-(q) are repeated for each of a plurality of chips to be attached to said substrate.

6. The chip attach method of claim 5, wherein for each of said plurality of chips said lowering step (p) further includes holding said chip pickup against said chip for a period of time sufficient to allow said chip to adhesively attach to said substrate.

7. A method for accurately positioning a plurality of die on a substrate without reference to a substrate fudicial mark, said substrate having a first physical reference feature and a first one of said plurality of die having a second physical reference feature, said method comprising the steps of:

(a) positioning said first one of said die relative to said first physical feature of said substrate; and

(b) subsequent said step (a), positioning the remaining die of said plurality of die on said substrate relative to said second physical reference feature of said first die positioned on said substrate, wherein only said first die is positioned on said substrate relative to said substrate first physical reference feature while the reaming chips are placed on said substrate relative to said first die'"'"'s second physical reference feature.

8. The die positioning method of claim 7, wherein said first physical reference feature of said substrate used in said positioning step (a) comprises a corner of said substrate.

9. The die positioning method of claim 7, wherein said first die'"'"'s second physical reference feature employed in said step (b) comprises an interconnection pad located on an upper surface of said first die.

10. Apparatus for accurately positioning a plurality of die on a substrate without reference to a substrate fiducial mark, said apparatus comprising:

first means for positioning a first one of said die relative to a physical feature of said substrate, said first die having a first physical feature to facilitate the subsequent positioning of said plurality of die on said substrate; and

second means operatively associated with and responsive to said first means for accurately positioning the remaining die of said plurality of die on said substrate relative to the physical feature on an upper surface of the first die positioned on said substrate by said first means, wherein said chips are each accurately positioned relative to one another within the tolerances of said second positioning means'"'"' capability to recognize said first die'"'"'s first physical feature.

11. The die positioning apparatus of claim 10, wherein said substrate physical feature used by said first positioning means comprises a corner of said substrate.

12. The die positioning apparatus of claim 10, wherein said first die'"'"'s physical feature used by said second positioning means comprises an interconnection pad located on the upper surface of said first die.

13. The die positioning apparatus of claim 10, wherein said first positioning means positions said first die relative to said substrate physical feature with reference to said first physical feature of said first die, and wherein said second positioning means uses said first physical feature of said first die to position the remaining die of said plurality of die.

14. The die positioning apparatus of claim 13, wherein said first physical feature of said first die comprises an interconnection pad on the upper surface of said first die.

15. Apparatus for accurately positioning a die relative to a substrate having a fiducial mark thereon, said apparatus comprising:

a high accuracy XY table, said table having a first rotational adjustment stage and a second rotational adjustment stage, said first rotational adjustment stage comprising a die alignment stage for holding and aligning a die relative to XY table motion based on a physical feature of the die, said second rotational adjustment stage comprising a substrate alignment stage, said substrate alignment stage including means for holding said substrate having said fiducial mark thereon;

locating means operatively associated with said high accuracy XY table for locating the fiducial mark on said substrate;

a die pickup operatively associated with said high accuracy XY table for removing said die from said die alignment stage and for placing said die on said substrate; and

control processing means coupled to said first and second rotational adjustment stages of said XY table, said locating means and said die pickup, for controlling the respective alignment of said substrate and said die, and transfer of said die to the desired location on said substrate relative to said located fiducial mark using said die pickup.

16. The die positioning apparatus of claim 15, further comprising a bridging structure disposed over said XY table, said bridging structure supporting said locating means and said die pickup.

17. The die positioning apparatus of claim 16, wherein said die pickup includes two motion stages, a first motion stage being reciprocally mounted to said bridging structure for Z-axis movement relative to said XY table, said first motion stage having a lower stop affixed thereto, and a second motion stage mounted to said first stage for reciprocal Z-axis movement relative to said first stage, said lower first stage stop being affixed so as to contact and raise said second stage with the rising of said first motion stage, said second stage having a die attach mechanism secured thereto, said attach mechanism comprising a vacuum pickup tool.

18. The die positioning apparatus of claim 15, wherein said control processing means includes memory means for storing the desired location on said substrate of said die relative to said fiducial mark.

19. The die positioning apparatus of claim 18, wherein multiple die are to be accurately positioned on said substrate using said apparatus, and wherein said memory means stores for each of said multiple die the desired location for the die on the substrate relative to said fiducial mark.

20. The die positioning apparatus of claim 19, wherein said XY table includes vacuum hold means for releasably holding said die during said die alignment stage.

21. Apparatus for accurately positioning a die having a first physical feature relative to a substrate having a second physical feature, said apparatus comprising:

a high accuracy XY table, said table having a first rotational adjustment stage and a second rotational adjustment stage, said first rotational adjustment stage comprising a die alignment stage for holding and aligning the die relative to XY table motion based on said first physical feature of the die, said second rotational adjustment stage comprising a substrate alignment stage, said substrate alignment stage including means for holding said substrate;

locating means operatively associated with said high accuracy XY table for locating said second physical feature on said substrate;

a die pickup operatively associated with said high accuracy XY table for removing said die from said die alignment stage and for placing said die on said substrate; and

control processing means coupled to said first and second rotational adjustment stages of said XY table, said locating means and said die pickup, for controlling the respective alignment of said substrate and said die, and transfer of said die to the desired location on said substrate relative to said located substrate second physical feature.

22. The die positioning apparatus of claim 21, wherein said control processing includes memory means for storing the desired location on said substrate of said die relative to said located second physical feature.

23. The die positioning apparatus of claim 22, wherein said die comprises a first die and multiple additional die are positioned on said substrate using said apparatus, and wherein said control means positions each one of said multiple additional die on said substrate relative to the first die positioned thereon.

24. The die positioning apparatus of claim 23, wherein each of said multiple additional die is positioned on said substrate relative to the first physical feature of said first die positioned on said substrate.

25. The die positioning apparatus of claim 24, wherein said first physical feature of the first die comprises an interconnection pad positioned on an upper surface of said first die.

26. The die positioning apparatus of claim 24, wherein said control means includes memory means for storing the desired position on said substrate of each of the multiple additional die relative to said first physical feature of the first positioned die.