Analog-to-digital converter circuit

• US 5,146,223 A
• Filed: 11/01/1991
• Issued: 09/08/1992
• Est. Priority Date: 11/02/1990
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Muto, Hiroyasu
• Primary Examiner(s): Logan, Sharon D.
• Application Number:
  US07/786,540
• Time in Patent Office: 312 Days
• Field of Search: 341/118, 341/155, 341/120
• US Class Current: 341/118
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

The offset from the ideal value for the bias voltage to be added to the input signal to the A/D converter and the offset from the ideal value of the average voltage in the analog signal are detected. The detected offset is substracted from the output data of the A/D converter. Alternately, the bias voltage may be changed by the detected offset so that the average voltage of the input signal to the A/D converter is equal to the ideal value.

Claims

1. An A/D converter circuit comprising:

bias voltage summing means for adding a bias voltage to an analog signal;

A/D converter means for digitizing the output analog signal from said bias voltage summing means in the range between the low and high reference voltages;

offset detection means for detecting the offset by subtracting the ideal average voltage of the analog signal and the ideal value of the bias voltage from the average value of output samples from said A/D converter means; and

subtraction means for deriving the output by subtracting the output data of said offset detection circuit from the output data of said A/D converter means.

2. An A/D converter circuit comprising:

bias voltage summing means for adding a bias voltage to an analog signal;

bias voltage generation means for generating the bias voltage;

A/D converter means for digitizing the output analog signal from said bias voltage summing means in the range between low and high reference voltages;

offset detection means for detecting offset by subtracting the ideal average voltage of the analog signal and the ideal value of the bias voltage from the average value of the output samples from said A/D converter means; and

correction means for supplying the output of said offset detection means to either one of said bias voltage generation circuit or said bias voltage summing circuit to correct the bias voltage so that the average voltage of the input signal to said A/D converter means is equal to the ideal value.

3. An A/D converter circuit comprising:

bias voltage summing means for adding a bias voltage to an analog signal;

A/D converter means for digitizing the output analog signal from said bias voltage summing means in the range between low and high reference voltage;

means for outputting the accumulated value of a predetermined number (N) of samples;

means for obtaining the average value by dividing the accumulated value by N;

means for detecting the offset voltage value by subtracting the ideal average voltage value of the analog signal and the ideal value of the bias voltage from the average value; and

subtraction means for outputting the subtraction of the output data of said offset detection circuit from the output data of said A/D converter means.

4. The A/D converter circuit of claim 3 wherein the correction is made by subtraction operation using continuous offset voltage values of the samples subsequent to the predetermined number (N).

5. The A/D converter circuit of claim 3 wherein the correction is made by subtraction operation using offset voltage value of a predetermined number of samples subsequent to the predetermined number (N).

6. An A/D converter circuit comprising:

bias voltage summing means for adding a bias voltage to an analog signal;

bias voltage generation means for generating the bias voltage;

A/D converter means for digitizing the output analog signal from said bias voltage summing means in the range between low and high reference voltages;

means for outputting the accumulated value of a predetermined number (N) of samples;

means for obtaining the average value by dividing the accumulated value by N;

means for detecting the offset voltage value by subtracting the ideal average voltage value of the analog signal and the ideal value of the bias voltage from the average value; and

correction means for supplying the output of said offset detection means to either one of said bias voltage generation circuit or said bias voltage summing circuit to correct the bias voltage so that the average voltage of the input signal to said A/D converter means is equal to the ideal value.

7. An A/D converter circuit comprising:

bias voltage summing means for adding a bias voltage to an analog signal;

bias voltage generation means for generating the bias voltage;

A/D converter means for digitizing the output analog signal from said bias voltage summing means in the range between low and high reference voltages;

means for outputting the accumulated value of a predetermined number (N) of samples;

means for obtaining the average value by dividing the accumulated value by N;

means for detecting the offset voltage value by subtracting the ideal average voltage value of the analog signal and the ideal value of the bias voltage from the average value;

D/A converting means for converting the obtained offset voltage into an analogue signal and supplying the converted signal to one of said bias voltage generating circuit and said bias voltage adding circuit; and

means, in response to the output of said D/A converting means, for compensating the bias voltage of one of said bias voltage generating circuit and said bias voltage adding circuit.

8. An A/D converting method comprising the steps of:

adding a bias voltage to an analog signal;

digitizing the added analog signal in the range between the low and high reference voltages;

detecting an offset by subtracting the ideal average voltage of the analog signal and the ideal value of the bias voltage from the average value of said digitized data; and

deriving the output by subtracting said detected offset from said digitized data.