Semiconductor package utilizing edge connected semiconductor dice

• US 5,146,308 A
• Filed: 10/05/1990
• Issued: 09/08/1992
• Est. Priority Date: 10/05/1990
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Cloud, Eugene H., Chance, Randal W.
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US07/593,177
• Time in Patent Office: 704 Days
• Field of Search: 357/55, 357/75, 357/80, 357/68, 357/65
• US Class Current: 257/782
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/08237 the bonding area connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

Die bond locations on a semiconductor die are formed as vertical inserts along the edge of the die. The vertical inserts are isolated from substrate and are exposed by a wafer saw process, in which dice are singulated from a wafer. The configuration offers the advantages of a more efficient layout, allowing the entire top surface of the die to be passivated, a better contact configuration, and more convenient assembly for packaging.

Claims

1. Semiconductor integrated circuit apparatus comprising:

a) a supporting substrate having a top surface;

b) a plurality of semiconductor dies mounted to said supporting substrate, each of the plurality of semiconductor dies having at least one exposed edge, the plurality of semiconductor dies being mounted to said supporting substrate such that said exposed edge on each die abuts the top surface of the supporting substrate;

c) the semiconductor dies each having a semiconductor substrate and circuitry within the die;

d) a plurality of depressions in said semiconductor dies, the depressions extending to the exposed edge;

e) the semiconductor substrate being a first conductivity type;

f) one or more wells in said substrate of a second conductivity type, said depressions being within said wells;

g) bond pads disposed within said depressions, the bond pads being connected to said circuitry within the die to form bond pad locations for external electrical connection to the semiconductor dies;

h) a first group of contacts on said supporting substrate, contacting said bond pads, and thereby establishing connections to said circuitry within the die; and

i) the supporting substrate establishing electrical contact with the bond locations formed along said exposed edge.

2. Semiconductor integrated circuit apparatus of claim 1, further comprising:

said depressions being formed to extend into the semiconductor dies more than 1/500 the thickness of the substrate, but less than 1/2 the thickness of the substrate.

3. Semiconductor integrated circuit apparatus of claim 1, further comprising:

said depressions being formed to extend into the semiconductor dies more than 1/100 the thickness of the substrate, but less than about 1/5 the thickness of the substrate.

4. The semiconductor integrated circuit apparatus of claim 1, wherein said first conductivity type is p and said second conductivity type is n.

5. Semiconductor integrated circuit apparatus of claim 1, further comprising:

a) a resistor, the resistor including substrate material within one of said wells; and

b) said depressions being within said wells.

6. Semiconductor integrated circuit apparatus of claim 5, wherein:

a) said material within one of said wells being a second conductivity type; and

b) said first conductivity type is p and said second conductivity type is n.

7. Semiconductor integrated circuit apparatus of claim 1, further comprising:

a) a layer of polysilicon in at least one of said depressions between the substrate and the bond pad located within said depression and above said layer of polysilicon; and

b) said polysilicon being doped to a predetermined level.

8. Semiconductor integrated circuit apparatus of claim 1, further comprising:

a layer of dielectric in at least one of said depressions between the substrate and the bond pad located within said recess.

9. Semiconductor integrated circuit apparatus comprising:

a) a supporting substrate having a top surface;

b) a plurality of semiconductor dies mounted to said supporting substrate, each of the plurality of semiconductor dies having at least one exposed edge, the plurality of semiconductor dies being mounted to said supporting substrate such that said exposed edge on each die abuts the top surface of the supporting substrate;

c) the semiconductor dies each having a semiconductor substrate and circuitry within the die;

d) a plurality of depressions in said semiconductor dies, the depressions extending to the exposed edge;

e) bond pads disposed within said depressions, the bond pads being connected to said circuitry within the die to form bond pad locations for external electrical connection to the semiconductor dies;

f) a first group of contacts on said supporting substrate, contacting said bond pads, and thereby establishing connections to said circuitry within the die;

g) the supporting substrate establishing electrical contact with the bond locations formed along said exposed edge;

h) a layer of polysilicon in at least one of said depressions between the substrate and the bond pad located within said depression and above said layer of polysilicon; and

i) said polysilicon being doped to a predetermined level.

10. Semiconductor integrated circuit apparatus of claim 9, further comprising:

said depressions being formed to extend into the semiconductor dies more than 1/500 the thickness of the substrate, but less than 1/2 the thickness of the substrate.

11. Semiconductor integrated circuit apparatus of claim 9, further comprising:

said depressions being formed to extend into the semiconductor dies more than 1/100 the thickness of the substrate, but less than 1/5 the thickness of the substrate.

12. Semiconductor integrated circuit apparatus of claim 9, further comprising:

a layer of dielectric in at least one of said depressions between the substrate and the bond pad located within said recess.

13. Semiconductor integrated circuit apparatus comprising:

a) a supporting substrate having a top surface;

b) a plurality of semiconductor dies mounted to said supporting substrate, each of the plurality of semiconductor dies having at least one exposed edge, the plurality of semiconductor dies being mounted to said supporting substrate such that said exposed edge on each die abuts the top surface of the supporting substrate;

c) the semiconductor dies each having a semiconductor substrate and circuitry within the die;

d) a plurality of depressions in said semiconductor dies, the depressions extending to the exposed edge;

e) bond pads disposed within said depressions, the bond pads being connected to said circuitry within the die to form bond pad locations for external electrical connection to the semiconductor dies;

f) a layer of dielectric in at least one of said depressions between the substrate and the bond pad located within said recess;

g) a first group of contacts on said supporting substrate, contacting said bond pads, and thereby establishing connections to said circuitry within the die; and

h) the supporting substrate establishing electrical contact with the bond locations formed along said exposed edge.

14. Semiconductor integrated circuit apparatus of claim 13, further comprising:

said depressions being formed to extend into the semiconductor dies more than 1/500 the thickness of the substrate, but less than 1/2 the thickness of the substrate.

15. Semiconductor integrated circuit apparatus of claim 13, further comprising:

said depressions being formed to extend into the semiconductor dies more than 1/100 the thickness of the substrate, but less than 1/5 the thickness of the substrate.