Differential capacitor structure and method

• US 5,146,389 A
• Filed: 07/22/1991
• Issued: 09/08/1992
• Est. Priority Date: 07/22/1991
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Ristic, Ljubisa, Dunn, William C.
• Primary Examiner(s): GRIFFIN, DONALD
• Application Number:
  US07/733,920
• Time in Patent Office: 414 Days
• Field of Search: 361/320, 361/321, 361/283, 73/517 R, 73/517 AV, 73/516, 29/25.42
• US Class Current: 361/283.3
• CPC Class Codes: G01D 5/2417 by varying separation
• CPC Class Codes: G01P 2015/0828 the mass being of the paddle type being suspended at one of its longitudinal ends
• CPC Class Codes: G01P 2015/0882 for providing damping of vibrations
• CPC Class Codes: H01L 28/40 Capacitors

Abstract

A differential capacitor structure includes a first static conductive layer and a second static conductive layer not electrically coupled to the first static conductive layer. A dynamic conductive layer is suspended between the first and second static conductive layers.

Claims

1. A differential capacitor structure comprising:

a first static semiconductive layer;

a second static semiconductive layer not electrically coupled to said first layer; and

a dynamic semiconductive layer suspended between and not electrically coupled to said first and second layers.

2. The structure of claim 1 wherein the first layer is disposed on a substrate, said substrate being non-conductive or electrically isolated from said first layer.

3. The structure of claim 1 wherein protective layers are disposed on the first and second layers adjacent the dynamic layer.

4. The structure of claim 1 wherein one or both of the second and dynamic layers include perforations.

5. The structure of claim 1 wherein additional mass is disposed on the dynamic layer.

6. The structure of claim 1 wherein the dynamic layer is supported by a single pillar.

7. The structure of claim 1 wherein voltage is applied to the first layer to create electrostatic forces and test the structure.

8. The structure of claim 1 wherein the first layer comprises a plurality non-electrically coupled segments thereby allowing a plurality of capacitors in the single structure.

9. The structure of claim 8 wherein the plurality of capacitors is employed to balance the structure.

10. A differential capacitor structure comprising:

a substrate;

a first static polysilicon layer disposed on said substrate;

a second static polysilicon layer disposed a distance above and not electrically coupled to said first layer; and

a dynamic polysilicon layer suspended between and not electrically coupled to said first and second layers.

11. The structure of claim 10 wherein the substrate is non-conductive or electrically isolated from said first layer.

12. The structure of claim 11 wherein silicon nitride protective layers are disposed on the first and second layers adjacent the dynamic layer.

13. The structure of claim 12 wherein one or both of the second and dynamic layers include perforations.

14. The structure of claim 13 wherein the dynamic layer is supported by a single pillar.

15. The structure of claim 14 wherein additional mass is disposed on the dynamic layer.

16. The structure of claim 15 wherein voltage is applied to the first layer to create electrostatic forces and test the structure.

17. The structure of claim 16 wherein the first layer comprises a plurality of non-electrically coupled segments thereby allowing a plurality of differential capacitors in the single structure.

18. The structure of claim 17 wherein the plurality of differential capacitors is employed to balance the structure.

19. A differential capacitor structure comprising:

a substrate;

a first static conductive layer;

a second static conductive layer not electrically coupled to said first layer;

a dynamic conductive layer suspended between and not electrically coupled to said first and second layers; and

wherein said structure is fabricated by forming said first static layer on said substrate, forming a first sacrificial layer on said first static layer, forming said dynamic layer on said first sacrificial layer, forming a second sacrificial layer on said dynamic layer, forming said second static layer on said second sacrificial layer and removing said first and second sacrificial layers.

20. The structure of claim 19 wherein the substrate is non-conductive or electrically isolated from said first static layer.

21. The structure of claim 20 wherein protective layers are disposed on the first and second layers adjacent the dynamic layers.

22. The structure of claim 20 wherein one or both of the second and dynamic layers include perforations.

23. The structure of claim 20 wherein additional mass is disposed on the dynamic layer.

24. The structure of claim 20 wherein the dynamic layer is supported by a single pillar.

25. The structure of claim 20 wherein voltage is applied to the first static-layer to create electrostatic forces and test the structure.

26. The structure of claim 20 wherein the first static layer comprises a plurality of non-electrically coupled segments thereby allowing a plurality of differential capacitors in the single structure.

27. The structure of claim 26 wherein the plurality of differential capacitors is employed to balance the structure.

28. The structure of claim 20 wherein the first static, second static and dynamic layers comprise polysilicon and the sacrificial layers comprise phosphosilicate glass.

29. The structure of claim 28 wherein the sacrificial layers are removed by selectively etching said sacrificial layers with an HF solution.

30. The structure of claim 20 further comprising a first metal layer formed following the formation of a third sacrificial layer on the second static layer.

31. A method of fabricating a differential capacitor structure comprising the steps of:

providing a substrate;

forming a first static conductive layer on said substrate;

forming a first sacrificial layer on said first conductive layer;

forming a dynamic conductive layer on said first sacrificial layer;

forming a second sacrificial layer on said dynamic layer;

forming a second static conductive layer on said second sacrificial layer; and

selectively removing said sacrificial layers.

32. The method of claim 31 wherein the providing a substrate step includes providing a non-conductive substrate or a substrate to be electrically isolated from the first conductive layer.

33. The method of claim 32 further including the steps of forming protective layers on the first and second conductive layers adjacent the dynamic layer.

34. The method of claim 32 wherein the first and second conductive layers, the dynamic layer and the sacrificial layers are each patterned and etched following their respective formation so that said dynamic layer is suspended between said first and second conductive layers and so that neither said first or second conductive layers or said dynamic layer are electrically coupled.

35. The method of claim 34 wherein the patterning and etching of the second conductive and dynamic layers includes patterning and etching perforations into one or both of said layers.

36. The method of claim 34 further including the step of forming additional mass on the dynamic layer.

37. The method of claim 34 further comprising, prior to the selectively removing step, the steps of:

forming a third sacrificial layer on the second conductive layer;

patterning and etching said third sacrificial layer; and

forming at least one metal layer on exposed portions of one or more conductive layers.

38. The method of claim 34 wherein the first and second conductive layers and the dynamic layer comprise polysilicon and the sacrificial layers comprise phosphosilicate glass.

39. The method of claim 38 wherein the selectively removing step includes etching away the sacrificial layers with an HF solution.